ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 12
ql6325-4pt280c
Manufacturer Part Number
ql6325-4pt280c
Description
Combining Performance, Density, And Embedded Ram
Manufacturer
QuickLogic Corp
Datasheet
1.QL6325-4PT280C.pdf
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Eclipse Family Data Sheet Rev. F
Clock Networks
Global Clocks
There are eight global clock networks in the Eclipse device family. Global clocks can drive logic cell, I/O, and
RAM blocks in the device. Five global clocks have access to a Quad Net (local clock network) connection with
a programmable connection to the register inputs. Global clock pins are 2.5 V, LVCMOS2, compliant.
www.quicklogic.com
Figure 9: Global Clock Methodology
CLK Pin
Quad Net
Global Clock Net
© 2007 QuickLogic Corporation
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