ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 21

• Manufacturer Part Number: ql6325-4pt280c
• Description: Combining Performance, Density, And Embedded Ram
• Manufacturer: QuickLogic Corp

AC Characteristics at V
The AC Specifications are provided from
provided from
© 2007 QuickLogic Corporation
Symbol
t
t
t
RESET
CWLO
CWHI
t
t
t
t
t
t
t
SET
SW
RW
PD
SU
CO
HL
Combinatorial Delay of the longest path:
circuit to output
Setup time:
active clock edge
Hold time:
active clock edge
Clock to out delay:
active clock edge.
Clock High Time:
Clock Low Time:
Set Delay:
consequently “set” (high)
Reset Delay:
is consequently “reset” (low)
Set Width:
Reset Width:
Figure 16
time between when the flip flop is “set” (high) and when the output is
time the synchronous input of the flip flop must be stable after the
time that the SET signal remains high/low
time the synchronous input of the flip flop must be stable before the
to
time between when the flip flop is “reset” (low) and when the output
time that the RESET signal remains high/low
Figure
required minimum time that the clock stays low
required minimum time the clock stays high
the amount of time taken by the flip flop to output after the
CC
21.
= 2.5 V, TA = 25° C (K = 1.00)
Figure 16: Eclipse Logic Cell
Table 13
Table 13: Logic Cells
Parameter
to
time taken by the combinatorial
Table
21. Logic Cell diagrams and waveforms are
Eclipse Family Data Sheet Rev. F
0.205 ns
0.231 ns
0.46 ns
0.46 ns
0.3 ns
0.3 ns
Min.
0 ns
www.quicklogic.com
-
-
-
Value
0.427 ns
0.585 ns
0.658 ns
1.01 ns
Max.
-
-
-
-
-
-
•
•
•
•
•
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