ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 10

• Manufacturer Part Number: ql6325-4pt280c
• Description: Combining Performance, Density, And Embedded Ram
• Manufacturer: QuickLogic Corp

10
•
•
•
•
•
•
Eclipse Family Data Sheet Rev. F
For registered control operation, the array logic drives the D input of the OE cell register which in turn drives
the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered
signal to be driven to the three-state control.
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to
be used for registered feedback into the logic array.
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular
routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/Os. The
CLK and RESET signals share common lines, while the clock enables for each register can be independently
controlled. I/O interface support is programmable on a per bank basis.
configurations.
Each I/O bank is independent of other I/O banks and each I/O bank has its own V
inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to
which I/O standards can be supported within a given bank. Only standards that share a common V
INREF can be shared within the same bank (e.g., PCI and LVTTL).
www.quicklogic.com
VCCIO 6
INREF 7
VCCIO 7
INREF 6
VCCIO 5
PLL
PLL
VCCIO 0
Embedded RAM Blocks
Embedded RAM Blocks
Figure 7: Multiple I/O Banks
INREF 5
INREF 0
Fabric
VCCIO 4
VCCIO 1
Figure 7
INREF 4
illustrates the I/O bank
CCIO
INREF 1
PLL
PLL
© 2007 QuickLogic Corporation
and INREF supply
CCIO
INREF 3
VCCIO 2
INREF 2
VCCIO 3
and