ql6325-4pt280c QuickLogic Corp, ql6325-4pt280c Datasheet - Page 37

• Manufacturer Part Number: ql6325-4pt280c
• Description: Combining Performance, Density, And Embedded Ram
• Manufacturer: QuickLogic Corp

Recommended Unused Pin Terminations for the Eclipse Devices
All unused, general purpose I/O pins can be tied to V
Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the
Placement Editor, choose Constraint
The rest of the pins should be terminated at the board level in the manner presented in
NOTE:
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CLK/PLLIN<x>
Signal Name
PLLOUT<x>
PLLRST<x>
IOCTRL<y>
INREF<y>
x -> number, y -> alphabetical character.
For low power unused PLL output pins can be connected to V
input buffer never floats, otherwise PLL output pins can be left unconnected. Utilized PLL output
pins that route the PLL clock outside of the chip should not be tied to either V
Any unused pins of this type must be connected to either V
Any unused clock pins should be connected to V
If a PLL module is not used, then the associated PLLRST<x> must be connected to V
normal operation, use it as needed. If PLLs are not used, the associated PLLRST pin must be
connected to the same voltage as V
If an I/O bank does not require the use of INREF signal the pin should be connected to GND.
IOCTRL(G)
IOCTRL(H)
V CCIO
V CCIO
INREF(H)
INREF(G)
IO(G)
IO(H)
(H)
(G)
Table 24: Recommended Unused Pin Terminations
Figure 35: I/O Banks with Relevant Pins
Fix Placement in the Option pull-down menu of SpDE.
IO BANK A
IO BANK F
Recommended Termination
CC
CC
PLL (2.5 V or GND).
, GND, or HIZ (high impedance) internally using the
IO BANK B
IO BANK E
CC
or GND.
CC
CC
Eclipse Family Data Sheet Rev. F
or GND.
or GND so that their associated
INREF(C)
IO(C)
INREF(D)
IO(D)
V CCIO (C)
IOCTRL(C)
V CCIO (D)
IOCTRL(D)
Table
CC
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or GND.
24.
CC
; under
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