XC7300FM Xilinx, XC7300FM Datasheet - Page 8

• Manufacturer Part Number: XC7300FM
• Description: XC7300 CMOS EPLD Family
• Manufacturer: Xilinx

maximum integrated dose the XC7300 EPLD can be
exposed to without damage is 7000 W • s/cm
mately one week at 12,000 W/cm
Design Recommendations
For proper operation, all unused input and I/O pins must
be connected to a valid logic level (High or Low). The rec-
ommended decoupling for all V
using high-speed (tantalum or ceramic) capacitors.
Use electrostatic discharge (ESD) handling procedures
with the XC7300 EPLDs to prevent damage to the device
during programming, assembly, and test.
Design Security
Each member of the XC7300 family has a multibit security
system that controls access to the configuration pro-
grammed into the device. This security scheme uses mul-
tiple EPROM bits at various locations within the EPROM
array to offer a higher degree of design security than other
EPROM and fused-based devices. Programmed data
within EPROM cells is invisible–even when examined
under a microscope–and cannot be selectively erased.
The EPROM security bits, and the device configuration
data, reset when the device is erased.
High-Volume Production Programming
The XC7300 family offers flexibility for low-volume proto-
types as well as cost-effectiveness for high-volume pro-
duction. The designer can start with ceramic window
package parts for prototypes, ramp up initial production
using low-cost plastic parts programmed in-house, and
then shift into high-volume production using Xilinx factory
programmed and tested devices.
The Xilinx factory programmed concept offers significant
advantages over competitive masked PLDs, or ASIC
redesigns:
• No redesign is required – Even though masked devices
• Devices are factory tested – Factory-programmed
• Shipments are delivered fast – Production shipments
are advertised as timing compatible, subtle differences
in a chip layout can mean system failure.
devices are tested as part of the manufacturing flow,
insuring high-quality products.
can begin within a few weeks, eliminating masking
delays and qualification requirements.
CC
2
pins should total 1 F
.
2
, or approxi-
2-8
For factory programming procedures, contact your local
Xilinx representative.
XEPLD Development System
The designer can create, implement, and verify digital
logic circuits for EPLD devices using the Xilinx XEPLD
Development System. Designs can be represented as
schematics consisting of XEPLD library components, as
behavioral descriptions, or as a mixture of both. The
XEPLD translator maps the design quickly and automati-
cally onto a chosen EPLD device, produces documenta-
tion for design analysis and creates a programming file to
configure the device.
The following lists some of the XEPLD Development Sys-
tem features.
• Familiar design approach similar to TTL and PLD
• Converts netlist to fuse map in minutes using a ’486
• Interfaces to standard third-party CAE schematics,
• Schematic library with familiar and powerful TTL-like
• Predictable timing even before design entry, using
Timing simulation using Viewsim, OrCAD VST, and other
tools controlled by the Xilinx Design Manager (XDM)
program
Timing Model
Timing within the XC7300 EPLDs is accurately deter-
mined using external timing parameters from the device
data sheet, using a variety of CAE simulators, or with the
timing model shown in Figure 8.
The timing model is based on the fixed internal delays of
the XC7300 architecture which consists of four basic
parts: I/O Blocks, the UIM, Fast Function Blocks and
High-Density Function Blocks. The timing model identifies
the internal delay paths and their relationships to ac char-
acteristics. Using this model and the ac characteristics,
designers can easily calculate the timing information for a
particular EPLD.
techniques
PC or workstation platform
simulation tools, and behavioral languages
components, including PLDs and ALUs
library components and Boolean equations