M29DW324DB70N1E NUMONYX [Numonyx B.V], M29DW324DB70N1E Datasheet - Page 10

• Manufacturer Part Number: M29DW324DB70N1E
• Description: 32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block) 3V Supply Flash Memory
• Manufacturer: NUMONYX [Numonyx B.V]

M29DW324DT, M29DW324DB
SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
Protect pin provides two functions. The V
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the Dou-
ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When V
protects the two outermost boot blocks; Program
10/50
IH
PP/
. When BYTE is Low, V
Figure 2., Logic
Write Protect (V
IH
PP
, all other pins are ignored.
/Write Protect is Low, V
IL
, this pin behaves as an address
Diagram, and
PP
/WP). The
IH
, this pin behaves as a
IL
, these pins are not
Table 1., Signal
IL
, the memory
V
PP
PP
/Write
func-
and Erase operations in these blocks are ignored
while V
at V
When V
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase oper-
ations can now modify the data in these blocks un-
less the blocks are protected using Block
Protection.
When V
ory automatically enters the Unlock Bypass mode.
When V
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
Never raise V
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the V
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
most boot blocks will remain protected even if RP
is at V
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
goes High, V
Read and Bus Write operations after t
t
Output section,
Block Temporary Unprotect AC
more details.
Holding RP at V
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
PLPX
RHEL
PHPHH
IH
ID
to V
. After Reset/Block Temporary Unprotect
, whichever occurs last. See the Ready/Busy
VHVPP
.
PP
ID
.
PP
PP
PP
PP
.
/Write Protect pin must not be left floating
PP
/Write Protect is Low, even when RP is
/Write Protect is raised to V
/Write Protect is High, V
/Write Protect returns to V
, see
and from V
IH
PP
PP
PP
, the memory will be ready for Bus
/Write Protect pin and the V
/WP is at V
Table 19.
/Write Protect to V
ID
Figure 17.
will temporarily unprotect the
IH
to V
PP
PP
and
to V
ID
IL
.
, then the two outer-
must be slower than
IH
Figure 16., Reset/
must be slower
Waveforms, for
IH
IL
, the memory
IH
PP
, for at least
PP
or V
the mem-
from any
PHEL
PP
IL
from
nor-
SS
or