M29DW324DB70N1E NUMONYX [Numonyx B.V], M29DW324DB70N1E Datasheet - Page 48

• Manufacturer Part Number: M29DW324DB70N1E
• Description: 32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block) 3V Supply Flash Memory
• Manufacturer: NUMONYX [Numonyx B.V]

M29DW324DT, M29DW324DB
REVISION HISTORY
Table 33. Document Revision History
48/50
07-May-2003
18-Sep-2003
07-Nov-2003
19-Dec-2003
10-Dec-2004
23-Mar-2004
30-Aug-2004
14-Mar-2004
19-Apr-2002
08-Apr-2003
25-Jun-2003
07-Oct-2003
Date
Version
-01
2.0
2.1
3.0
3.1
3.2
3.3
3.4
4.0
5.0
6.0
7.0
Document written
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0).
Revision History moved to end of document.
When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Logic diagram corrected.
TFBGA48, 6x8mm, 0.8mm pitch package added. Identification Current I
Table
parameters and notes added to
Endurance
APPENDIX
read the Extended Memory Block. Extended Memory Block Verify Code row added to
Tables
Address modified in
Status Register
Ordering Information
Table
Figure
Outline” corrected.
Document promoted from Preliminary Data to full Datasheet status. Packing option added
to
Status of Ready/Busy signal for Erase Suspend Operation modified in
Register
Figures
Table 18., Toggle and Alternative Toggle Bits AC
Note 1 of
Figures
and 2 added.
Figure 8.
Block Protection Status read modified in the Auto Select command section.
V
V
Architecture option updated in
Block Protect/Unprotect code updated in
Customer Lockable Extended Block mechanism modified in
MEMORY
APPENDIX D., BLOCK
Technique section and Note 2 added below
Protect
Introduction of
Section
TFBGA63 package removed.
Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in
Table 8., Status Register
RB updated in
Fast Program Commands
Unlock Bypass Command.
CC
PP
Table
and I
minimum value updated in
14.,
20.,
3
18.,
Flowchart.
14
14
, DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
22.,
and 4,
Bits.
PP
renamed and modified; Note added.
Table 28., Device Geometry
48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data
DC
BLOCK.
and 15, Toggle and Alternative Toggle Bits Mechanisms modified and Notes 1
and 15, Toggle and Alternative Toggle Bits Mechanisms added.
Cycles.
48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package
C.,
test conditions updated in
Ordering Information
Table 18., Toggle and Alternative Toggle Bits AC
Characteristics. Erase Suspend Latency time and Data Retention
STATUS REGISTER
Table 8., Status Register
EXTENDED MEMORY
Bus Operations, BYTE = V
Bits. V
Auto Select
Scheme.
SS
PROTECTION, updated: Note 1 added in the In-System
Bits.
pin connection to ground clarified. Note added to
restructured and updated.
updated.
Table 22., Ordering Information
Table 12., Operating and AC Measurement
Table
Command. Chip Erase Address modified in
Scheme.
Revision Details
section clarified.
7.,
Definition, modified.
Table 14., DC
BLOCK, added.
Bits.
APPENDIX
Program, Erase Times and Program, Erase
IL
Figure 22., In-System Equipment Group
and
Bus Operations, BYTE = V
Characteristics, added.
Characteristics.
B.,
Auto Select Command
Table 29.
APPENDIX C., EXTENDED
Scheme.
Characteristics, modified.
Table 8., Status
ID
added.
removed from
Table
Conditions.
IH
Table
. Bank
sued to
22.,
8.,
and