M29DW324DB70N1E NUMONYX [Numonyx B.V], M29DW324DB70N1E Datasheet - Page 5

• Manufacturer Part Number: M29DW324DB70N1E
• Description: 32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block) 3V Supply Flash Memory
• Manufacturer: NUMONYX [Numonyx B.V]

SUMMARY DESCRIPTION
The M29DW324D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.
The device features an asymmetrical block archi-
tecture. The M29DW324D has an array of 8 pa-
rameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read op-
erations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in pro-
gram or erase mode. The bank architecture is
summarized in
Parameter Blocks at the top of the memory ad-
dress space while the M29DW324DB locates the
Parameter Blocks starting from the bottom.
M29DW324D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated com-
mand. The Extended Block can be protected and
so is useful for storing security information. How-
Figure 2. Logic Diagram
A0-A20
BYTE
RP
W
G
E
21
Table 2.
M29DW324DB
M29DW324DT
V CC
V SS
M29DW324DT locates the
V PP /WP
15
DQ0-DQ14
DQ15A–1
RB
AI06867B
ever the protection is irreversible, once protected
the protection cannot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm) and
TFBGA48 (6x8mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).
Table 1. Signal Names
A0-A20
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
V
V
NC
CC
SS
PP
/WP
M29DW324DT, M29DW324DB
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
V
Ground
Not Connected Internally
PP
/Write Protect
5/50