M29W004B-100N1TR STMICROELECTRONICS [STMicroelectronics], M29W004B-100N1TR Datasheet - Page 17

• Manufacturer Part Number: M29W004B-100N1TR
• Description: 4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 15B. Write AC Characteristics, Write Enable Controlled
(T
Notes: 1. Sample only, not 100% tested.
Chip Erase (CE) Instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tion of the erase by the P/E.C., Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
t
PHPHH
Symbol
A
t
t
WHRL
PHWL
t
t
t
t
t
t
t
t
t
t
t
WHGL
t
VCHEL
t
WLWH
DVWH
WHDX
WHEH
WHWL
= 0 to 70 C, –20 to 85 C or –40 to 85 C)
WLAX
GHWL
AVWL
ELWL
PLPX
AVAV
2. This timing is for Temporary Block Unprotection operation.
(1,2)
(1)
(1)
t
t
t
t
t
BUSY
t
t
Alt
t
WPH
VIDR
t
t
t
t
t
t
OEH
t
VCS
RSP
WC
WP
CS
DS
DH
CH
AH
RP
AS
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
V
Write Enable High to Output Enable Low
RP Rise Time to V
RP Pulse Width
Program Erase Valid to RB Delay
RP High to Write Enable Low
CC
High to Chip Enable Low
Parameter
ID
after the sixth rising edge of W or E output the
status register status bits.
During the execution of the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
V
Min
500
500
CC
120
50
50
30
50
50
0
0
0
0
0
0
4
= 2.7V to 3.6V
-120
M29W004T / M29W004B
Max
90
M29W004T, M29W004B
V
Min
500
500
CC
150
65
65
35
65
50
0
0
0
0
0
0
4
= 2.7V to 3.6V
-150
Max
90
Unit
17/30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s