M29W004B-100N1TR STMICROELECTRONICS [STMicroelectronics], M29W004B-100N1TR Datasheet - Page 2

• Manufacturer Part Number: M29W004B-100N1TR
• Description: 4 Mbit 512Kb x8, Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W004T, M29W004B
Figure 2. TSOP Pin Connections
Warning: NC = Not Connected.
DESCRIPTION (Cont’d)
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
Table 2. Absolute Maximum Ratings
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
2/30
V
(A9, E, G, RP)
Symbol
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
A16
A15
A14
A13
A12
A11
A18
V
T
T
NC
RP
RB
V
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
A9
A8
A7
A6
A5
A4
A3
A2
A1
T
BIAS
IO
W
STG
CC
A
(2)
(2)
1
10
11
20
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, E, G, RP Voltage
M29W004T
M29W004B
AI02064
40
31
30
21
Parameter
A17
V SS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V CC
V CC
NC
DQ3
DQ2
DQ1
DQ0
G
V SS
E
A0
(1)
(3)
Table 1. Signal Names
cycles of commands to a Command Interface using
standard microprocessor write timings.
The device is offered in TSOP40 (10 x 20mm)
package.
Organisation
The M29W004 is organised as 512K x8. The mem-
ory uses the address inputs A0-A18 and the Data
Input/Outputs DQ0-DQ7. Memory control is pro-
vided by Chip Enable E, Output Enable G and Write
Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
A0-A18
DQ0-DQ7
E
G
W
RP
RB
V
V
CC
SS
Address Inputs
Data Input/Outputs, Command Inputs
Chip Enable
Output Enable
Write Enable
Reset / Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground
–0.6 to 5
–0.6 to 5
–0.6 to 13.5
–40 to 85
–50 to 125
–65 to 150
Value
ID
) temporarily unprotects
Unit
V
V
V
C
C
C