MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 3

• Manufacturer Part Number: MPC9351D
• Description: Low Voltage PLL Clock Driver
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
TIMING SOLUTIONS
ABSOLUTE MAXIMUM RATINGS a
GENERAL SPECIFICATIONS
PIN CONFIGURATION
PCLK, PCLK
TCLK
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
QA
QB
QC0, QC1
QD0 - QD4
VCCA
VCC
GND
FUNCTION TABLE
Symbol
Symbol
V OUT
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
I OUT
V CC
HBM
C PD
V TT
V IN
MM
C IN
I IN
T S
LU
REF_SEL
PLL_EN
Control
FSELA
FSELB
FSELC
FSELD
Pin
OE
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch–Up
Power Dissipation Capacitance
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
Supply
Characteristics
Default
I/O
0
1
0
0
0
0
0
Characteristics
Freescale Semiconductor, Inc.
Selects PCLK as reference clock
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
Outputs enabled
QA = VCO
QB = VCO
QC = VCO
QD = VCO
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VCC
VCC
Ground
For More Information On This Product,
Type
2
4
4
4
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2000
Min
200
200
Differential clock reference
Low voltage positive ECL input
Single ended reference clock signal or test clock
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock outputs
Bank D clock outputs
Positive power supply for the PLL
Positive power supply for I/O and core
Negative power supply
0
3
V CC
Min
-0.3
-0.3
-0.3
-55
Typ
4.0
10
B
2
Selects TCLK as reference clock
PLL enabled. The VCO output is routed to the
output dividers
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
QA = VCO
QB = VCO
QC = VCO
QD = VCO
Function
V CC +0.3
V CC +0.3
Max
150
4.6
Max
20
50
4
8
8
8
1
Unit
Unit
mA
mA
mA
pF
pF
V
V
V
V
V
V
C
MPC9351
Per output
Inputs
Condition
Condition
MOTOROLA