MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 7

• Manufacturer Part Number: MPC9351D
• Description: Low Voltage PLL Clock Driver
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Calculation of part-to-part skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9351 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (
resulting in a worst case timing uncertainty from input to any
output of -251 ps to 351 ps relative to TCLK (V CC =3.3V and
f VCO = 400 MHz):
t SK(PP) =
t SK(PP) =
TIMING SOLUTIONS
t SK(PP) = t ( ) + t SK(O) + t PD, LINE(FB) + t JIT( )
Table 8: Confidence Facter CF
Any Q Device 1
Any Q Device 2
TCLK Common
The MPC9351 zero delay buffer supports applications
This maximum timing uncertainty consist of 4
Due to the statistical nature of I/O jitter a RMS value (1
The feedback trace delay is determined by the board
QFB Device 1
QFB Device2
CF
1
2
3
4
5
6
Figure 3. MPC9351 max. device-to-device skew
Max. skew
s
s
s
s
s
s
Probability of clock edge within the distribution
[–50ps...150ps] + [–150ps...150ps] +
[(17ps
[–251ps...351ps] + t PD, LINE(FB)
@
t JIT( )
–3)...(17ps
+t SK(O)
–t ( )
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
+t ( )
t JIT( )
Freescale Semiconductor, Inc.
@
t SK(PP)
3)] + t PD, LINE(FB)
For More Information On This Product,
3
t PD,LINE(FB)
s
+t SK(O)
) is assumed,
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s
CF
) is
7
shown in the AC characteristic table for V CC =3.3V (17 ps
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC9351).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 4. and Figure 5. can be used to
derive a smaller I/O jitter number at the specific VCO
frequency, resulting in tighter timing limits in zero-delay mode
and for part-to-part skew t SK(PP) .
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
V CCA (PLL) power supply impacts the device characteristics,
for instance I/O jitter. The MPC9351 provides separate power
supplies for the output buffers (V CC ) and the phase-locked
loop (V CCA ) of the device.The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult
to minimize noise on the power supplies a second level of
isolation may be required. The simple but effective form of
isolation is a power supply filter on the V CCA pin for the
MPC9351. Figure 6. illustrates a typical power supply filter
scheme. The MPC9351 frequency and phase stability is
most susceptible to noise with spectral content in the 100kHz
to 20MHz range. Therefore the filter should be designed to
Figure 4. Max. I/O Jitter (RMS) versus frequency for
Figure 5. Max. I/O Jitter (RMS) versus frequency for
Above equation uses the maximum I/O jitter number
The MPC9351 is a mixed analog/digital product. Its analog
V CC =2.5V
V CC =3.3V
MPC9351
MOTOROLA