MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 8

• Manufacturer Part Number: MPC9351D
• Description: Low Voltage PLL Clock Driver
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MPC9351
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop across the series
filter resistor R F . From the data sheet the I CCA current (the
current sourced through the V CCA pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 2.325V (V CC =3.3V
or V CC =2.5V) must be maintained on the V CCA pin. The
resistor R F shown in Figure 6. “V CCA Power Supply Filter”
must have a resistance of 270
(V CC =2.5V) to meet the voltage drop criteria.
C F are defined by the required filter characteristics: the RC
filter should provide an attenuation greater than 40 dB for
noise whose spectral content is above 100 kHz. In the
example RC filter shown in Figure 6. “V CCA Power Supply
Filter”, the filter cut-off frequency is around 3-5 kHz and the
noise attenuation at 100 kHz is better than 42 dB.
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9351 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
MOTOROLA
The minimum values for R F and the and the filter capacitor
As the noise frequency crosses the series resonant point
The MPC9351 clock driver was designed to drive high
R F = 270 for V CC = 3.3V
R F = 9–10 for V CC = 2.5V
VCC
Figure 6. V CCA Power Supply Filter
R F
C F
33...100 nF
10 nF
W
C F = 1 F for V CC = 3.3V
C F = 22 F for V CC = 2.5V
Freescale Semiconductor, Inc.
(V CC =3.3V) or 9-10
For More Information On This Product,
VCCA
MPC9351
VCC
Go to: www.freescale.com
the
W
8
technique terminates the signal at the end of the line with a
50
thus only a single terminated line can be driven by each
output of the MPC9351 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 7. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9351 clock driver is effectively doubled due to its
capability to drive multiple lines.
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9351 output buffer is more than
sufficient to drive 50
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9351. The output waveform in Figure 8. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
IN
IN
This technique draws a fairly high level of DC current and
At the load end the voltage will double, due to the near
The waveform plots in Figure 8. “Single versus Dual Line
Figure 7. Single versus Dual Transmission Lines
resistance to V CC 2.
MPC9351
MPC9351
OUTPUT
OUTPUT
BUFFER
BUFFER
14
14
V L = V S ( Z 0
Z 0 = 50 || 50
R S = 36 || 36
R 0 = 14
V L = 3.0 ( 25
= 1.31V
R S = 36
R S = 36
R S = 36
transmission lines on the incident
series resistor plus the output
(R S +R 0 +Z 0 ))
(18+17+25)
Z O = 50
Z O = 50
Z O = 50
TIMING SOLUTIONS
OutA
OutB0
OutB1