MPC9351D FREESCALE [Freescale Semiconductor, Inc], MPC9351D Datasheet - Page 5

• Manufacturer Part Number: MPC9351D
• Description: Low Voltage PLL Clock Driver
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

a.
b.
a.
b.
TIMING SOLUTIONS
DC CHARACTERISTICS (V CC = 2.5V
AC CHARACTERISTICS (V CC = 2.5V
Symbol
V CMR a
t JIT(PER)
t PLZ, HZ
t PZL, ZH
t JIT(CC)
Symbol
Z OUT
V CMR b
I CCQ
I CCA
t JIT( )
V OH
t LOCK
V PP
V OL
C PD
f refDC
V IH
C IN
t sk(o)
V IL
f VCO
f MAX
I IN
V PP
t ( )
tr, tf
t r , t f
BW
f ref
DC
V CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR range
and the input swing lies within the V PP (DC) specification.
The MPC9351 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line
to a termination voltage of V TT . Alternatively, the device drives up to two 50 series terminated transmission lines per output.
AC characteristics apply for parallel output termination of 50 to V TT
V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V CMR range
and the input swing lies within the V PP (AC) specification. Violation of V CMR or V PP impacts static phase offset t ( ) .
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output Impedance
Input Leakage Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Input Frequency
VCO Frequency
Maximum Output Frequency
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
PLL closed loop bandwidth
Cycle-to-cycle jitter
Single Output Frequency Configuration
Period Jitter
Single Output Frequency Configuration
I/O Phase Jitter
Maximum PLL Lock Time
Characteristics
Characteristics
Freescale Semiconductor, Inc.
PCLK to EXT_FB
TCLK to EXT_FB
For More Information On This Product,
PCLK, PCLK
PCLK, PCLK
100 – 200 MHz
5%, T A = –40 to 85 C)
5%, T A = –40 to 85 C) a
50 – 100 MHz
PCLK, PCLK
PCLK, PCLK
25 – 50 MHz
2 feedback
4 feedback
8 feedback
2 feedback
4 feedback
8 feedback
4 feedback
4 feedback
2 output
4 output
8 output
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Min
250
1.7
1.0
1.8
48.75
–100
47.5
Min
100
200
100
500
1.2
0.1
50
25
50
25
25
45
5
0
17 - 20
Typ
4.0 – 15.0
4.0
3.0
10
2.0 – 7.0
0.7 – 2.0
6.0 – 25
Typ
8.0
50
50
50
10
V CC + 0.3
V CC -0.6
Max
0.7
0.6
5.0
1.0
150
V CC -0.6
51.75
1000
+100
+300
Max
52.5
200
100
400
200
100
150
1.0
1.0
1.0
50
50
75
55
12
12
22
15
Unit
mV
mA
mA
pF
pF
W
V
V
V
V
V
A
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
mV
ms
ns
ps
ps
ps
ns
ns
ns
ps
ps
ps
%
%
%
%
V
LVCMOS
LVCMOS
LVPECL
LVPECL
I OH =-15 mA b
I OL = 15 mA
V IN = V CC or GND
Per Output
V CCA Pin
All V CC Pins
LVPECL
LVPECL
0.7 to 1.7V
0.6 to 1.8V
–3dB point of
PLL transfer
characteristic
RMS value
RMS value
RMS value
PLL locked
PLL locked
Condition
MPC9351
Condition
MOTOROLA