AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 10

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, f
otherwise noted.
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Sync Input Timing Diagram
AD6657A
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
Description
See Figure 3 for details
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
See Figure 60 for details, except where noted
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge (not pictured in
Figure 60)
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge (not pictured in
Figure 60)
S
= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
SYNC
CLK+
t
Figure 3. SYNC Input Timing Requirements
SSYNC
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t
HSYNC
Min
2
2
40
2
2
10
10
10
10
Typ
0.24
0.40
Data Sheet
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns