AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 33

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

Data Sheet
Addr.
(Hex)
0x24
0x25
Digital Feature Control Registers
0x3A
0x3C
0x3E
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled
in Register 0x00 to Register 0xFF, see the
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Sync Mode
Bit 2 selects the mode of the clock divider sync function. When
Bit 2 is low, continuous sync mode is enabled. When Bit 2 is
high, the clock divider is reset on the next rising edge of the
sync signal. Subsequent rising edges of the sync signal are
ignored.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low
to conserve power.
Register
Name
BIST
signature LSB
(local)
BIST signa-
ture MSB
(local)
Sync control
(global)
NSR control
(local)
NSR tuning
word
(local)
(MSB)
Bit 7
Open
Open
Open
Bit 6
Open
Open
Open
AN-877 Application
Bit 5
Open
Open
Equations for the tuning word are dependent on the NSR mode.
Bit 4
Open
MODE
pin
disable
0 =
MODE
pin used
1 =
MODE
pin dis-
abled
BIST Signature[15:8]
Rev. 0 | Page 33 of 36
BIST Signature[7:0]
See the Noise Shaping Requantizer section.
Bit 3
Open
NSR tuning word
NSR Control (Register 0x3C)
Bits[7:5]—Reserved
Bit 4—MODE Pin Disable
Bit 4 specifies whether the selected channels are to be controlled
by the MODE pin. Local registers act on the channels that are
selected by the channel index register (Address 0x05).
Bits[3:1]—NSR Mode
Bits[3:1] determine the bandwidth (BW) mode of the NSR.
When Bits[3:1] are set to 000, the NSR is configured for a 22%
BW mode that provides enhanced SNR performance over 22%
of the sample rate. When Bits[3:1] are set to 001, the NSR is
configured for a 33% BW mode that provides enhanced SNR
performance over 33% of the sample rate. When Bits[3:1] are
set to 010, the NSR is configured for a 36% BW mode that pro-
vides enhanced SNR performance over 36% of the sample rate.
Bit 0—NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)
is set.
000 = 22% BW mode
001 = 33% BW mode
010 = 36% BW mode
Bit 2
Clock divider
sync mode
0 = conti-
nuous
1 = next sync
mode, next
rising edge of
sync resets
clock divider
NSR mode
Bit 1
Clock
divider
sync
enable
0 = off
1 = on
(LSB)
Bit 0
Master
sync
enable
0 = off
1 = on
NSR
enable
0 = off
1 = on
(used only
if
Bit 4 = 1;
otherwise
ignored)
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x1C
AD6657A
Comments
Read only.
Read only.
Control
register to
synchronize
the clock
divider.
Noise
shaping
requantizer
(NSR)
controls.
NSR
frequency
tuning word.