AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 24

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

DIGITAL OUTPUTS
The
LVDS outputs using a DRVDD supply voltage of 1.8 V. The
output bits are DDR LVDS as shown in Figure 2. Applications
that require the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
As described in the
High Speed ADCs via SPI, the data format can be selected for
offset binary or twos complement when using the SPI control.
TIMING
The
nine clock cycles. Data outputs are available one propagation
delay (t
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AD6657A
AD6657A
AD6657A
PD
) after the rising edge of the clock signal.
output drivers are configured to interface with
provides latched data with a latency of
AN-877 Application
Condition (V)
< −V
= −V
= 0
= +V
> +V
REF
REF
REF
REF
− 0.5 LSB
− 1.0 LSB
− 0.5 LSB
Note, Interfacing to
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
Rev. 0 | Page 24 of 36
Minimize the length of the output data lines and minimize the
loads placed on them to reduce transients within the
because these transients can degrade converter dynamic per-
formance.
The lowest typical conversion rate of the
At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The
intended for capturing the data in an external register. The
output data for Channel A and Channel C is valid when DCO
is high; the output data for Channel B and Channel D is valid
when DCO is low (see Figure 2).
AD6657A
provides a data clock output (DCO) signal
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
AD6657A
Data Sheet
AD6657A
is 40 MSPS.