AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 3

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

Data Sheet
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are used.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
digital data rate (DDR) is 400 Mbps. These outputs are set at
1.8 V LVDS and support ANSI-644 levels.
The
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces component
cost and complexity compared with traditional analog techniques
or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board level system testing.
The
144-ball, 10 mm × 10 mm chip scale package ball grid array
AD6657A
AD6657A
receiver digitizes a wide spectrum of IF frequencies.
is available in a Pb-free, RoHS compliant,
AD6657A
AD6657A
to be used in
can achieve
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(CSP_BGA) that is specified over the industrial temperature
range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
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Four analog-to-digital converters (ADCs) are contained in
a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball
CSP_BGA package.
Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 65 MHz at 185 MSPS.
LVDS digital output interface configured for low cost
FPGA families.
230 mW per ADC core power consumption.
Operation from a single 1.8 V supply.
Standard SPI that supports various product features and
functions, such as data formatting (offset binary or twos
complement), NSR, power-down, test modes, and voltage
reference mode.
On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
AD6657A