AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 31

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr.
(Hex)
Chip Configuration Registers
0x00
0x01
Channel Index and Transfer Registers
0x05
0xFF
ADC Function Registers
0x08
0x0B
0x0C
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Channel
index
Transfer
Power modes
Clock divide
(global)
Shuffle mode
(local)
(MSB)
Bit 7
Open
Enable
output
port for
Channel C
and
Channel D
Open
Open
Open
Open
Bit 6
LSB first
Enable
output
port for
Channel A
and
Channel B
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(global)
0 = full
power-
down
1 =
standby
Open
000 = 0 input clock cycles delayed
010 = 2 input clock cycles delayed
001 = 1 input clock cycle delayed
Clock divide phase
Bit 4
1
Open
Open
Open
Open
AD6657A
8-bit chip ID, Bits[7:0]
Rev. 0 | Page 31 of 36
= 0x7B (default)
Bit 3
1
Channel D
enable
Open
Open
Open
Bit 2
Soft reset
Channel C
enable
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB first
Channel B
enable
Open
Shuffle mode enable
00 = shuffle disabled
01 = shuffle enabled
00 = normal operation
01 = full power-down
Internal power-down
10 = standby
mode (local)
(default)
(LSB)
Bit 0
Open
Channel A
enable
SW
transfer
1 = on
0 = off
(default)
Default
Value
(Hex)
0x18
0x7B
0xCF
0x00
0x00
0x00
0x01
AD6657A
Comments
Nibbles are
mirrored so
that LSB first
or MSB first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register 0x05
must be set.
Read only.
Bits are set to
determine
which
channel on
the chip
receives the
next write
command;
applies to
local
registers.
Synchro-
nously
transfers
data from
the master
shift register
to the slave.
Determines
generic
modes of
chip opera-
tion.
Enables or
disables
shuffle
mode.