AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 12

• Manufacturer Part Number: AD6657ABBCZ
• Description: Quad IF Receiver
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
A5, A8, B5 to B8, D4 to
D9, E2 to E11
A1, A4, A9, A12, B1, B2,
B4, B9, B11, B12, C2, C3,
C10, C11, D3, D10, E1,
E12, F1 to F12
H1 to H12
G1 to G12
A7
A6
C12
D12
D11
A11
A10
B10
A2
A3
B3
C1
D1
D2
K7
J7
M7
L7
K8
J8
M8
L8
K9
J9
AD6657A
M
G
A
B
C
D
E
H
K
F
J
L
DRGND
DRVDD
D0–CD
D0+CD
D1–CD
D1+CD
AGND
AGND
VIN+D
VIN–D
AGND
AGND
1
Mnemonic
AVDD
AGND
DRVDD
DRGND
CLK+
CLK−
VIN+A
VIN−A
VCMA
VIN+B
VIN−B
VCMB
VIN+C
VIN−C
VCMC
VIN+D
VIN−D
VCMD
D0+AB
D0−AB
D1+AB
D1−AB
D2+AB
D2−AB
D3+AB
D3−AB
D4+AB
D4−AB
DRGND
DRVDD
D2–CD
D2+CD
D3–CD
D3+CD
VIN+C
AGND
AGND
VCMD
AVDD
AGND
2
DRGND
DRVDD
D4–CD
D4+CD
D5–CD
D5+CD
VIN–C
VCMC
AGND
AGND
AVDD
AGND
3
Type
Supply
Ground
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
DRGND
DRVDD
D6+CD
D7+CD
D6–CD
D7–CD
AGND
AGND
AGND
AVDD
AVDD
CSB
4
Figure 4. Pin Configuration (Top View)
DRGND
DRVDD
D8–CD
D8+CD
D9–CD
D9+CD
AGND
AVDD
AVDD
AVDD
AVDD
SDIO
5
Rev. 0 | Page 12 of 36
Description
Analog Power Supply. 1.8 V nominal.
Analog Ground.
Digital Output Driver Supply. 1.8 V nominal.
Digital Output Driver Ground.
ADC Clock Input—True.
ADC Clock Input—Complement.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Common-Mode Level Bias Output for Analog Input Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Input Channel B.
Differential Analog Input Pin (+) for Channel C.
Differential Analog Input Pin (−) for Channel C.
Common-Mode Level Bias Output for Analog Input Channel C.
Differential Analog Input Pin (+) for Channel D.
Differential Analog Input Pin (−) for Channel D.
Common-Mode Level Bias Output for Analog Input Channel D.
Channel A and Channel B LVDS Output Data 0—True.
Channel A and Channel B LVDS Output Data 0—Complement.
Channel A and Channel B LVDS Output Data 1—True.
Channel A and Channel B LVDS Output Data 1—Complement.
Channel A and Channel B LVDS Output Data 2—True.
Channel A and Channel B LVDS Output Data 2—Complement.
Channel A and Channel B LVDS Output Data 3—True.
Channel A and Channel B LVDS Output Data 3—Complement.
Channel A and Channel B LVDS Output Data 4—True.
Channel A and Channel B LVDS Output Data 4—Complement.
DCO–CD
DCO+CD D1+AB
D10–CD
D10+CD
DRGND
DRVDD
AGND
AVDD
SCLK
AVDD
AVDD
CLK–
6
DRGND
DRVDD
D0–AB
D0+AB
D1–AB
PDWN
AVDD
AVDD
AVDD
AGND
CLK+
7
DRGND
DRVDD
D2–AB
D2+AB
D3–AB
D3+AB
AGND
AVDD
AVDD
SYNC
AVDD
AVDD
8
DRGND
DRVDD
D4–AB
D4+AB
D5–AB
D5+AB
AGND
AGND
MODE
AGND
AVDD
AVDD
9
DRGND
DRVDD
D6–AB
D6+AB
D7–AB
D7+AB
VIN–B
VCMB
AGND
AGND
AGND
AVDD
10
DRGND
DRVDD
D8–AB
D8+AB
D9+AB DCO+AB
D9–AB
VIN+B
AGND
AGND
VCMA
AGND
AVDD
11
DCO–AB
D10–AB
D10+AB
DRGND
DRVDD
AGND
AGND
VIN+A
VIN–A
AGND
AGND
12
Data Sheet