AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet - Page 7

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AD6657ABBCZ

Manufacturer Part Number
AD6657ABBCZ
Description
Quad IF Receiver
Manufacturer
AD [Analog Devices]
Datasheet
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, f
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUT/OUTPUT (SDIO)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
1
2
2
S
= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 7 of 36
Min
0.2
AGND − 0.3
1.2
0
−10
−10
8
AGND
1.2
AGND
−100
−100
12
1.22
0
−10
40
1.22
0
−92
−10
1.22
0
−10
38
CMOS/LVDS/LVPECL
Typ
0.9
10
4
CMOS
0.9
16
1
26
2
26
2
26
5
Max
3.6
AVDD + 0.2
2.0
0.8
+10
+10
12
AVDD
AVDD
0.6
+100
+100
20
2.1
0.6
+10
132
2.1
0.6
−135
+10
2.1
0.6
+10
128
AD6657A
Unit
V
V p-p
V
V
V
µA
µA
pF
V
V
V
V
µA
µA
pF
V
V
µA
µA
pF
V
V
µA
µA
pF
V
V
µA
µA
pF

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