MC68HC705J MOTOROLA [Motorola, Inc], MC68HC705J Datasheet - Page 114

• Manufacturer Part Number: MC68HC705J
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Multifunction Timer Module
9.5.2 Timer Counter Register
Technical Data
114
Address:
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Reset:
1. At 2-MHz bus, 4-MHz XTAL, 0.5 s per cycle
Read:
Write:
RT1:RT0
0 0
0 1
1 0
1 1
$0009
TMR7
Bit 7
0
Table 9-1. Real-Time Interrupt Rate Selection
Multifunction Timer Module
Figure 9-4. Timer Counter Register (TCR)
2
2
2
2
17
of Cycles
14
15
16
= Unimplemented
Number
TMR6
to RTI
= 131,072
= 16,384
= 32,768
= 65,536
6
0
TMR5
Figure
5
0
Period
16.4 ms
32.8 ms
65.5 ms
8.2 ms
RTI
9-4.
TMR4
4
0
(1)
2
to COP Reset
TMR3
2
2
2
20
17
18
19
3
0
of Cycles
Number
= 1,048,576
= 131,072
= 262,144
= 524,288
MC68HC705J1A — Rev. 4.0
TMR2
2
0
TMR1
COP Timeout
1
0
131.1 ms
262.1 ms
524.3 ms
Period
65.5 ms
MOTOROLA
TMR0
(1)
Bit 0
0