MC68HC705J MOTOROLA [Motorola, Inc], MC68HC705J Datasheet - Page 74

• Manufacturer Part Number: MC68HC705J
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Resets and Interrupts
Technical Data
74
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request.
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/V
low-level triggered. Port A external interrupt pins can be positive-edge
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in
is holding an external interrupt pin low.
PA0
IRQ
PA3
PA2
PA1
PP
Figure 4-4
pin can be negative-edge triggered only or negative-edge and
(MOR)
PIRQ
Resets and Interrupts
Figure 4-4. External Interrupt Logic
IRQ VECTOR FETCH
shows the IRQ/V
Figure
LEVEL-SENSITIVE TRIGGER
IRQR
RESET
V
(MOR LEVEL BIT)
DD
D
4-5, is latched as long as any source
CK
LATCH
CLR
IRQ
PP
PP
Q
pin can latch another interrupt
pin interrupt logic.
MC68HC705J1A — Rev. 4.0
IRQF
IRQE
MOTOROLA
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST