MC68HC705J MOTOROLA [Motorola, Inc], MC68HC705J Datasheet - Page 37
MC68HC705J
Manufacturer Part Number
MC68HC705J
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705J.pdf
(162 pages)
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2.5 RAM
MC68HC705J1A — Rev. 4.0
MOTOROLA
Addr.
$001E
$0019
$001F
$07F0
$07F1
Mask Option Register
Register Name
NOTE:
Unimplemented
Unimplemented
COP Register
See page 99.
See page 41.
Reserved
(COPR)
(MOR)
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. Before processing an interrupt, the central processor
unit (CPU) uses five bytes of the stack to save the contents of the CPU
registers. During a subroutine call, the CPU uses two bytes of the stack
to store the return address. The stack pointer decrements when the CPU
stores a byte on the stack and increments when the CPU retrieves a byte
from the stack.
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Reset:
Reset:
Read:
Read:
Write:
Write:
SOSCD
Bit 7
R
EPMSEC OSCRES
= Unimplemented
6
R
Memory
5
R
R = Reserved
Unaffected by reset
SWAIT
4
R
SWPDI
3
R
PIRQ
2
R
LEVEL
1
R
Technical Data
Memory
COPEN
COPC
Bit 0
R
0
RAM
37