MC68HC705J MOTOROLA [Motorola, Inc], MC68HC705J Datasheet - Page 53

• Manufacturer Part Number: MC68HC705J
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

3.6.1.3 Direct
3.6.1.4 Extended
3.6.1.5 Indexed, No Offset
3.6.1.6 Indexed, 8-Bit Offset
MC68HC705J1A — Rev. 4.0
MOTOROLA
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or input/output
(I/O) location.
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE).
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Technical Data
Instruction Set
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