MC68HC705J MOTOROLA [Motorola, Inc], MC68HC705J Datasheet - Page 72

• Manufacturer Part Number: MC68HC705J
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Resets and Interrupts
4.3.2 External Reset
4.3.3 COP Watchdog Reset
4.3.4 Illegal Address Reset
Technical Data
72
A logic 0 applied to the RESET pin for 1 1/2 t
reset. A Schmitt trigger senses the logic level at the RESET pin.
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
An opcode fetch from an address not in random-access memory (RAM)
or erasable, programmable read-only memory (EPROM) generates a
reset.
Notes:
ADDRESS BUS
RESET pulse width
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
1. Internal clock, internal address bus, and internal data bus are not available externally.
INTERNAL
INTERNAL
INTERNAL
DATA BUS
CLOCK
RESET
Characteristic
Resets and Interrupts
Figure 4-3. External Reset Timing
Table 4-1. External Reset Timing
$07FE
t
RL
$07FE
$07FE
Symbol
$07FE
t
RL
NEW
PCH
cyc
$07FF
MC68HC705J1A — Rev. 4.0
generates an external
NEW
PCL
Min
1.5
NEW PC
DUMMY
Max
—
NEW PC
MOTOROLA
CODE
OP
Unit
t
cyc