FIN224AC_0611 FAIRCHILD [Fairchild Semiconductor], FIN224AC_0611 Datasheet - Page 8

• Manufacturer Part Number: FIN224AC_0611
• Description: uSerDes 22-Bit Bi-Directional Serializer/Deserializer
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
Deserializer Operation: DIRI = 0
Deserializer Operation: DIRI = 0
Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this
mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal
provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 = 1), all deserializer
output data pins are driven LOW until valid data is passed through the deserializer.
(Serializer Source:
CKREF = STROBE)
(Serializer Source:
CKREF does not = STROBE)
DP[1:24]
CKPO
Figure 10. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
CKSI
DP[1:24]
DSI
CKPO
CKSI
Figure 9. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
DSI
WORD n-2
b
WORD n-1
24
WORD n-2
b
WORD n-1
24
b
25
b
25
b
26
b
26
0
b
1
0
6 bit times
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer is different because it has
non-valid data bits sent between words. The duty cycle of CKP varies based on
the ratio of the frequency of the CKREF signal to the STROBE signal. The fre-
quency of the CKP signal is equal to the STROBE frequency. The falling edge of
CKP occurs six bit times after the data transition. The LOW time of the CKP sig-
nal is equal to 13 serial bit times. In modes 1 and 2, the CKP LOW time equals
half of the CKREF period of the serializer. In mode 3, the CKP LOW is equal to
the CKREF period. The CKP HIGH time is approximately equal to the STROBE
period, minus the CKP LOW time. Figure 10 is representative of a waveform that
could be seen when CKREF is not equal to STROBE. If CKREF was significantly
faster, additional non-valid data bits would occur between data words.
When the DIRI signal is asserted LOW, the device is configured as a deserial-
izer. Data is captured on the serial port and deserialized through use of the bit
clock sent with the data. The word boundary is defined in the actual clock and
data signal. Parallel data is generated at the time the word boundary is defined
in the actual clock and data signal. Parallel data is generated at the time the
word boundary is detected. The falling edge of CKP occurs approximately six bit
times after the falling edge of CKSI. The rising edge of CKP goes HIGH approxi-
mately 13 bit times after CKP goes LOW. The rising edge of CKP is generated
approximately 13 bit times later. When no embedded word boundary occurs, no
pulse on CKP is generated and CKP remains HIGH.
b
6
b
j
b
7
b
j+1
b
WORD n-1
8
13 bit times
WORD n-1
8
WORD n
b
WORD n
9
b
j+13
b
19
b
j+14
b
20
b
b
24
24
b
25
b
25
b
26
b
26
WORD n
WORD n+1
b
WORD n
1
WORD n+1
0
b
2
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