FIN324C_08 FAIRCHILD [Fairchild Semiconductor], FIN324C_08 Datasheet
FIN324C_08
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FIN324C_08 Summary of contents
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FIN324C 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Features Ultra-Low Operating Power: ~4mA at 5.44MHz Supports Dual-Display Implementations with RGB or Microcontroller Interface No External Timing Reference Needed SPI Mode Support Single Device Operates as a ...
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Ordering Information Operating Order Temperature Number Range FIN324CMLX -30 to 85°C FIN324CGFX -30 to 85°C For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Typical Application Diagram WE/PCLK 2 Baseband / Microprocessor Data/Control 24 © 2006 Fairchild Semiconductor Corporation ...
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Pin Definitions Pin I/O Type # Pins M/S CMOS IN 1 /RES CMOS IN 1 /STBY CMOS IN 1 SLEW CMOS IN 1 PAR/SPI CMOS IN 1 CKSEL CMOS IN 1 DP[17:0] CMOS I/O 18 CNTL[5:0] CMOS I/O 6 R/W ...
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Pin Assignments CKSEL 1 CKS+ 2 CKS- 3 Master VDDS 4 VDDA 5 M/S=1 DS- 6 Ground Pad DS+ 7 /RES 8 PAR/SPI 9 M/S 10 Figure 2. Master (M/S= CNTL[4] A R/W CNTL[2] or SDAT CNTL[5] ...
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System Control Pins (M/S) Master / Slave Selection: A given device can be configured as a master or slave device based on the state of the M/S pin. Table 1. Master/Slave M (PAR/SPI) SPI Mode Selection: The PAR/SPI ...
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CMOS I/O Signals System Control Signals The system control signals consist of M/S, /RES, /STBY(SLEW), PAR/SPI, and CKSEL. For connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. This allows these signals to ...
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Master/Slave READ Transactions Read transactions have two phases: The Read-Control Phase, where CNTL[5:0], R/W, CKSEL are transmitted to the deserializer; and the Read-Data Phase, where the DP[17:0] signals of the slave are read and transmitted back to the master device. ...
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Application Diagrams Baseband Processor /CS PCLK D4:G6 R,G,B[5:0] Hsync_D/C Vsync SD OE RESET VDDP1 GPIO /STBY /RES CKSEL Notes: Figure 6. Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display Baseband Processor A4 /WE B4 PCLK D4:G6 R,G,B[5:0] ...
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Application Diagrams Baseband Processor A4 /CS B4 PCLK D4:G6 R,G,B[5:0] C4 Hsync C3 Vsync D/C A2 SDAT B2 SCLK A1 VDDP1 GPIO /STBY G2 /RES B1 CKSEL Notes: Figure 8. Baseband Processor A4 /CS0 ...
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Application Diagrams Baseband Processor A4 /RE B4 /WE D4:G6 DATA[17:0] C4 ADDR C3 A3 /CS0 B3 /CS1 VDDP1 D3 GPIO F3 G3 /STBY G2 /RES B1 CKSEL0 CKSEL1 Notes: Figure 10. Additional Application Information Flex Cabling: The ...
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Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...
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Electrical Specifications Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Symbol Parameter DC Parallel I/O and Serial Characteristics V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output ...
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Symbol Parameter AC Deserializer Specifications CNTL[5:0],R/W to Falling t CS Edge of WCLKn t DP, CNTL to WCLK0 ↑ PDV-WR0 t DP, CNTL to WCLK1 ↑ PDV-WR1 t CNTL to WCLKn ↑ PDV-RD t Data, CNTL to SCLK ↑ PDV-SPI ...
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Symbol Parameter Allowed Skew between V t (18) VDD-SKEW and V DDA/S Minimum Reset Low Time t VDD-RES After V Stable DD /STBY Wait Time After t RES-STBY /RES ↑ /STBY to Active Edge of t DVALID Strobe Notes: 4. ...
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Typical Performance Characteristics Setup Time t S1 STROBE DP,CNTL Hold Time STROBE DP,CNTL Data Setup: CKSEL R/W=0 Figure 11. Master Write Setup and Hold Time t S-STRB STRB0 STRB1 SPI /CS CKSEL DP,CNTL Setup: CKSEL R/W=0 ...
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Typical Performance Characteristics STRBn CKS DS CNTL SLV WCLKn] DP SLV DP MSTR Setup: CKSEL R/W=1, PAR/SPI=1 DP[23:0],R/W STRBn Deserializer VDDP VDDS/A /RES /STBY STROBE Deserializer © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 (Continued) t PD-RD t ...
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Physical Dimensions 0.15 C PIN #1 IDENT 0.80 MAX 0.10 C 0.08 C 0.05 0.00 SEATING PLANE 0.50 (DATUM B) 0.50 NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION.. B. DIMENSIONS ...
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Physical Dimensions (Continued) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify ...
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Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 19 www.fairchildsemi.com ...