FIN324C_08 FAIRCHILD [Fairchild Semiconductor], FIN324C_08 Datasheet - Page 10

• Manufacturer Part Number: FIN324C_08
• Description: 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.1.2
Application Diagrams
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this
serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential Serial Wires the same length.
Do not allow noisy signals over or near differential serial wires.
Example: No CMOS traces over differential serial wires.
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Design goal of 100-ohms differential characteristic impedance.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales rep,
or contact Fairchild directly at
Baseband
Processor
DATA[17:0]
GPIO
CKSEL0
CKSEL1
/STBY
ADDR
/RES
/CS0
/CS1
/WE
/RE
Figure 10.
VDDP1
D4:G6
Notes:
C4
C3
D3
G3
G2
A4
B4
A3
B3
A2
B2
A1
F3
B1
(Continued)
1.
2.
3.
4.
5.
STRB0
STRB1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
VDDP VDDS/A
VDDP1
C2
[e-mail]
Dual display R/W Intel® interface.
Unused slave output pin must be NC (No Connection).
GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W.
Displays selected via the chip selects.
Pin numbers for BGA package.
Master
Dual R/W x86-Style Microcontroller Display Interface
VDDS/A
E2
CKS+
CKS-
GND
GND
GND
DS+
DS-
F2
D1
E1
G1
F1
E3
D2
C1
.
G1
F1
D1
E1
E3
D2
C1
10
GND
GND
GND
VDDP VDDS/A
C2
CKS+
CKS-
DS+
DS-
VDDP2
Slave
for applications notes or flex guidelines.
DP[17:0]
PAR/SPI
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
WCLK0
WCLK1
E2
SLEW
VDDS/A
VDDP
/RES
R/W
M/S
F2
A4
B4
D4:G6
C4
C3
A3
B3
A2 NC
B2
A1
D3
F3
G3
G2
B1
NC
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
/RE
/WE
DATA[7:0]
ADDR
/CS0
/RE
/WE
DATA[17:0]
ADDR
/CS1
Main Display
Sub- Display
Module 1
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