FIN3385_12 FAIRCHILD [Fairchild Semiconductor], FIN3385_12 Datasheet
FIN3385_12
Related parts for FIN3385_12
FIN3385_12 Summary of contents
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FIN3385 / FIN3386 Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer Features Operation -40°C to +85°C Low Power Consumption 20MHz to 85MHz Shift Clock Support ±1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size ...
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Block Diagrams Figure 1. FIN3385 Transmitter Functional Diagram © 2003 Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 Figure 2. FIN3386 Receiver Functional Diagram 2 www.fairchildsemi.com ...
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Transmitter Pin Configuration Figure 3. FIN3385 (28:4 Transmitter) Pin Assignments Pin Definitions Pin Names I/O Types TxIn I TxCLKIn I TxOut+ O TxOut- O TxCLKOut+ O TxCLKOut- O R_FB I /PwrDn I PLL PLL GND I LVDS ...
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Receiver Pin Configuration Figure 4. FIN3386 (28:4 Receiver) Pin Assignments Pin Definitions Pin Names I/O Types RxIn I RxIn+ I RxCLKIn- I RxCLKIn+ I RxOut O RxCLKOut- O /PwrDn I PLL PLL GND I LVDS V I ...
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Truth Tables Input / Output Truth Table Table 1. Inputs TxIn TxCLKIn Active Active Active LOW / HIGH / High Impedance Floating Active Floating Floating Don’t Care Don’t Care Notes: 1. The outputs of the transmitter or receiver remain in ...
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Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...
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Transmitter DC Electrical Characteristics Typical values are at T =25°C and with V A temperatures ranges, unless otherwise specified. Symbol Parameter Transmitter LVTTL Input Characteristics V Input HIGH Voltage IH V Input LOW Voltage IL V Input Clamp Voltage IK ...
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Transmitter AC Electrical Characteristics Typical values are at T =25°C and with V A temperatures ranges, unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock (TxCLKIn) HIGH Time TCH t Transmit Clock LOW Time TCL t ...
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Transmitter AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Transmitter Output Data Jitter (f=85MHz) t Transmitter Output Pulse Position of Bit 0 TPPB0 t Transmitter Output Pulse Position of Bit 1 TPPB1 t ...
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Receiver DC Characteristics Typical values are at T =25°C and with V A operating temperature ranges unless otherwise specified. Positive current values refer to the current flowing into device and negative values refer to current flowing out of pins. Voltages ...
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Receiver AC Characteristics Typical values are at T =25°C and with V A temperatures ranges, unless otherwise specified. Symbol Parameter t Receiver Clock Output (RxCLKOut) Period RCOP t RxCLKOut LOW Time RCOL t RxCLKOut HIGH Time RCOH t RxOut Valid ...
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Receiver AC Characteristics Typical values are at T =25°C and with V A temperatures ranges, unless otherwise specified. Symbol Parameter t Receiver Input Strobe Position of Bit 0 RSPB0 t Receiver Input Strobe Position of Bit 1 RSPB1 t Receiver ...
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Test Circuits Figure 5. Differential LVDS Output DC Test Circuit Notes: A: For all input pulses <=1ns includes all probe and jig capacitance. L Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and ...
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AC Loadings and Waveforms Note: 20. The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and LVTTL/CMOS I/O. Depending on the valid strobe edge of the transmitter, the TxCLKIn can be rising or falling edge data ...
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AC Loadings and Waveforms Figure 12. Receiver Setup/Hold and HIGH/LOW Times Note: 21. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with rising-edge strobe. The clock reference point is the time ...
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AC Loadings and Waveforms Figure 18. 28 Parallel LVTTL Inputs Mapped to Four Serial LVDS Outputs Note: 22. The information in this diagram shows the difference between clock out and the first data bit. A 2-bit cycle delay is guaranteed ...
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AC Loadings and Waveforms Note: 24 the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI). RSKM The minimum and maximum pulse position values are based on the bit position of each of the ...
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AC Loadings and Waveforms Figure 23. Transmitter Clock Out Jitter Measurement Setup Note: 25. Test setup considers no requirement for separation of RMS and deterministic jitter. Other hardware setups, such as Wavecrest boxes, can be used software ...
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AC Loadings and Waveforms Note: 29. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. © 2003 Fairchild ...
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Physical Dimensions 8.10 4.05 0.1 C -C- 0.50 Figure 27. 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. ...
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Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 21 www.fairchildsemi.com ...