FIN3385_12 FAIRCHILD [Fairchild Semiconductor], FIN3385_12 Datasheet - Page 9

• Manufacturer Part Number: FIN3385_12
• Description: Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Transmitter Output Data Jitter (f=85MHz)
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms
12. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
Symbol
t
t
t
t
t
t
t
t
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
TPLLS
t
JCC
after V
difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle
delay is guaranteed when the MSB is output from transmitter.
of less than 2ns.
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385 Transmitter Clock Out Jitter,
Cycle-to-Cycle, Figure 20
Transmitter Phase Lock Loop Set Time
CC
reaches 3.0V and /PwrDn pin is above 1.5V.
Parameter
(12)
(13)
9
(Continued)
Figure 20
f=40MHz
f=65MHz
f=85MHz
Figure 26
a
Condition

f

1
7
(12)
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
a-0.2
Min.
-0.2
Typ.
350
210
110
2a
3a
4a
5a
6a
0
a
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
Max.
a+0.2
370
230
150
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0.2
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ps