HC55120CM INTERSIL [Intersil Corporation], HC55120CM Datasheet - Page 12

• Manufacturer Part Number: HC55120CM
• Description: Low Power Universal SLIC Family
• Manufacturer: INTERSIL [Intersil Corporation]

Notes
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
10. Metallic to Longitudinal Balance - The metallic to longitudinal
11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
12. Two-Wire Return Loss - The 2-wire return loss is computed
13. Overload Level (4-Wire Port Off-Hook) - The overload level
2. Overload Level (Two-Wire Port, Off Hook) - The overload
3. Overload Level (Two-Wire Port, On Hook) - The overload
4. Longitudinal Impedance - The longitudinal impedance is
5. Longitudinal Current Limit (On-Hook Active) - On-Hook
6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
7. Longitudinal to Metallic Balance - The longitudinal to
8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
9. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
level is specified at the 2-wire port (V
the 4-wire receive port (E
Increase the amplitude of E
Reference Figure 1.
level is specified at the 2-wire port (V
the 4-wire receive port (E
the amplitude of E
Reference Figure 1.
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
are defined in Figure 2.
(TIP) L
(RING) L
where: E
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
is greater than 28mA RMS /Wire. Under this condition, SHD pin
remains low (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
is greater than 28mA RMS /Wire. Under this condition, SHD pin
remains high (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
metallic balance is computed using the following equation:
BLME = 20 log (E
Figure 4.
metallic to longitudinal balance is defined in this spec.
balance is computed using the following equation:
BLFE = 20 log (E
balance is computed using the following equation:
BMLE = 20 log (E
where: E
balance is computed using the following equation:
BFLE = 20 log (E
where: E
using the following equation:
r = -20 log (2V
the characteristic impedance of the line, nominally 600
(Reference Figure 6).
is specified at the 4-wire transmit port (V
source (E
(Reference Figure 7). Increase the amplitude of E
THD is measured at V
gain from the 2-wire port to the 4-wire port is equal to 1.
2-4
2-4
ZT
= 20log VTX/E
= 20log VTX/E
L
TR,
RX,
ZR
G
= V
= 1V
) at the 2-wire port, Z
= V
V
V
T
M
L
L
L
L
/A
RMS
R
and E
and E
/V
(Figure 3A) until the 2-wire longitudinal current
(Figure 3B) until the 2-wire longitudinal current
T
L
RX
/A
RX
L
TR
S
/V
/V
R
) where: Z
/V
(0Hz to 100Hz)
/V
TX
until 1% THD is measured at V
TR
L
L
RX
TR
TX
L
).
).
L
), E
), E
), where: E
), E
RX
RX
. Note the PTG pin is open, and the
are defined in Figure 5.
are defined in Figure 5.
4-12
RX
L
TR
). R
). R
RX
and V
until 1% THD is measured at V
D
= source is removed.
L
L
= 0
= The desired impedance; e.g.,
L
= 600 , I
=
= 20k
TX
L
TR
TR
ZT
, I
and V
are defined in Figure 4.
) with the signal source at
) with the signal source at
DCMET
, L
TX
ZR
DCMET
R
TR
) with the signal
, V
L
= 0mA. Increase
T
= 600
are defined in
, V
R
G
, A
18mA.
TR
until 1%
R
.
and A
TR
T
.
14. Overload Level (4-Wire Port On-Hook) - The overload level is
15. Output Offset Voltage - The output offset voltage is specified
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2-
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The
20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The
21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
specified at the 4-wire transmit port (V
(E
Increase the amplitude of E
Note the PTG pin is open, and the gain from the 2-wire port to
the 4-wire port is equal to 1.
with the following conditions: E
measured at V
4-wire frequency response is measured with respect to
E
The frequency response is computed using the following equation:
F
and compare to 1kHz reading.
V
wire frequency response is measured with respect to E
at 1.0kHz, E
frequency response is computed using the following equation:
F
and compare to 1kHz reading.
V
to 4-wire frequency response is measured with respect to
E
R
following equation:
F
and compare to 1kHz reading.
V
2-wire to 4-wire insertion loss is measured with respect to
E
R
L
where: V
The fuse resistors, R
insertion loss is for R
2-wire to 4-wire insertion loss is measured with respect to E
0dBm at 1.0kHz input signal, E
600 and is computed using the following equation:
L
where: V
The fuse resistors, R
insertion loss is for R
insertion loss is measured based upon E
input signal, E
computed using the following equation:
L
where: V
gain tracking is referenced to measurements taken for
E
R
G
-55dBm to -40dBm and compare to -10dBm reading.
V
2-4
2-4
4-2
G
2-4
4-2
4-4
G
TX
TR
RX
L
TX ,
L
G
L
TX
2-4
G
= 600 and is computed using the following equation:
= 600 and is computed using the following equation.
= 600 . The frequency response is computed using the
= 0dBm at 1.0kHz, E
= 0dBm at 1.0kHz input signal, E
) at the 2-wire port, Z
= -10dBm, 1.0kHz signal, E
, V
, R
, R
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 20 log (V
= 0dBm at 1.0kHz, E
= 20 log (V
R
TR
L
L
L
and V
and E
TX
TX
TR
and E
, R
, V
, V
, R
G
L
source removed from circuit, R
and E
G
TR
TR
L
TX
RX
TR
RX
TX
TR
TX
TX
TX
TR
and E
source removed from circuit, R
, R
, R
. E
TX
are defined in Figure 8.
are defined in Figure 8.
are defined in Figure 8.
/V
/E
/E
/V
/V
/E
L
L
G
G
/V
RX
TR
RX
TR
F
TR
F
RX
F1
F1
and E
and E
, R
, impact the insertion loss. The specified
, impact the insertion loss. The specified
RX
are defined in Figure 8.
TR
RX
), vary frequency from 300Hz to 3.4kHz
), vary frequency from 300Hz to 3.4kHz
), vary frequency from 300Hz to 3.4kHz
)
)
)
= R
= R
L
L
) vary amplitude -40dBm to +3dBm, or
are defined in Figure 8.
, V
= 20k
G
= 0V (VRX input floating), R
G
G
F2
G
F2
TX
source removed from circuit,
until 1% THD is measured at V
are defined in Figure 8. (Note:
are defined in Figure 8. (Note:
RX
G
= 0).
= 0).
RX
and Z
= 0, R
= 0 (VRX input floating), R
R
= 0 (VRX output floating),
RX
L
L
TX
=
L
are defined in Figure 7.
= 0 (VRX input floating),
) with the signal source
= 600 , Z
RX
(Reference Figure 7).
L
= 0dBm, 1.0kHz
= 600 . The
L
= 600 and is
L
=
RX
L
= 600 .
= 0dBm
and is
G
L
TX
=
=
.