HC55120CM INTERSIL [Intersil Corporation], HC55120CM Datasheet - Page 18

• Manufacturer Part Number: HC55120CM
• Description: Low Power Universal SLIC Family
• Manufacturer: INTERSIL [Intersil Corporation]

EXAMPLE:
Calculate Z
R
Z
Note: Some impedance models, with a series capacitor, will
cause the op-amp feedback to behave as an open circuit
DC. A resistor with a value of about 10 times the reactance
of the Z
frequency of interest (200Hz for example) can be placed in
parallel with the capacitor in order to solve the problem
(736k for a 10.8nF capacitor).
Calculating Tip and Ring Voltages
The on hook tip to ground voltage is calculated using
Equation 34. The minus 1.0 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I
the value of R
On hook Tip Voltage
The off hook tip to ground voltage is calculated using
Equation 35. I
allowed by the design and the value of R
in Equation 4.
Off hook Tip Voltage
The on hook ring to ground voltage is calculated using
Equation 36. The 1.5 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I
the value of R
On hook Ring Voltage
The calculation of the ring voltage with respect to ground in
the off hook condition is dependent upon whether the SLIC
is in current limit or not.
The off hook ring to ground voltage (in current limit) is
calculated using Equation 37. I
current limit and R
ring. The minus 0.2V is a correction factor for the 60k slope
in Figure 15.
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
V
V
V
T
P
TIP onhook
Z
TIP offhook
RING onhook
–
= 114k in series with 0.0108 F.
T
= 30 .
I
LOOP MAX
=
200 600
T
capacitor (2.16 F/200 = 10.8nF) at the low
T
to make Z
SAT(off)
=
LOOP(min)
SAT(off)
=
+
–
=
–
---------------------------------- -
j 2.16X10
1.0V
1V
R
V
L
P
BH
is the load resistance across tip and
–
is calculated in Equation 4.
is calculated in Equation 4.
+
+
1
TR
I
–
LOOP min
1.5V
is the minimum loop current
ISH-
4-18
= 600 in series with 2.16 F.
–
6
+
–
LIM
ISH
2 30
R
--------------------- -
SAToff
is the programmed loop
R
--------------------------
2
SAT off
R
--------------------------
2
SAT(off)
SAT off
2
SHD
SHD
is calculated
(0.6)) and
(0.6)) and
(EQ. 33)
(EQ. 34)
(EQ. 35)
(EQ. 36)
Off hook Ring Voltage in Current Limit
The off hook ring to ground voltage (not in current limit) is
calculated using Equation 38. The 1.5V results from the
SLIC self programming. I
current allowed by the design and the value of R
calculated in Equation 4.
Off hook Ring Voltage not in Current Limit
Layout Considerations
Systems with Dual Supplies (V
If the V
recommended that an additional diode be placed in series
with the V
on pin 8 of the device and cathode to the external supply.
This external diode will inhibit large currents and potential
damage to the SLIC, in the event the V
to GND. If V
required.
Floating the PTG Pin
The PTG pin is a high impedance pin (500k ) that is used to
program the 2-wire to 4-wire gain to either 0dB or -6dB.
If 0dB is required, it is necessary to float the PTG pin. The
PC board interconnect should be as short as possible to
minimize stray capacitance on this pin. Stray capacitance on
this pin forms a low pass filter and will cause the 2-wire to
4-wire gain to roll off at the higher frequencies.
If a 2-wire to 4-wire gain of -6dB is required, the PTG pin
should be grounded as close to the device as possible.
SPM Pin
For optimum performance, the PC board interconnect the
SPM pin should be as short as possible. If pulses metering
is not being used, then this pin should be grounded as close
to the device pin as possible.
RLIM Pin
The current limiting resistor R
RLIM pin as possible.
Layout of the 2-Wire Impedance Matching
Resistor Z
Proper connection to the ZT pin is to have the external Z
network as close to the device pin as possible.
The ZT pin is a high impedance pin that is used to set the
proper feedback for matching the impedance of the 2-wire
side. This will eliminate circuit board capacitance on this pin
to maintain the 2-wire return loss across frequency.
V
V
–
RING CL
RING NCL
I
LOOP MIN
BL
BH
supply is not derived from the V
=
BL
T
=
V
supply. The orientation of this diode is anode
V
TIP offhook
is derived from V
R
BH
P
+
1.5V
LOOP(min)
+
–
I
I
LOOP MAX
LOOP min
LIM
BH
needs to be as close to the
then this diode is not
is the minimum loop
BH
BH
R
and V
R
--------------------------
L
SAT off
BH
supply is shorted
–
0.2V
2
supply, it is
BL
SAT(off)
)
(EQ. 37)
(EQ. 38)
is
T