W25Q64DWSFIG WINBOND [Winbond], W25Q64DWSFIG Datasheet - Page 26

• Manufacturer Part Number: W25Q64DWSFIG
• Description: 1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
• Manufacturer: WINBOND [Winbond]

During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of t
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to
enter and operate in the QPI mode.
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register
bits are 0.
(IO
(IO
CLK
/CS
DO
DI
0
1
)
)
Mode 3
Mode 0
*
= MSB
0
1
Instruction (01h)
2
3
CLK
/CS
IO
IO
IO
IO
4
Figure 9a. Write Status Register Instruction (SPI Mode)
Figure 9b. Write Status Register Instruction (QPI Mode)
0
1
2
3
5
Mode 3
Mode 0
6
7
*
7
8
Instruction
0
6
01h
9
Status Register 1 in
High Impedance
5
10
1
- 26 -
4
4
5
6
7
SR1 in
11
2
3
12
0
1
2
3
3
2
13
12
13
14
15
SR2 in
4
1
14
10
11
8
9
5
0
15
15
*
Mode 3
Mode 0
16
14
17
Status Register 2 in
13
18
12
19
11
W25Q64DW
20
10
21
SHSL2
9
22
8
23
(See AC
Mode 3
Mode 0