W25Q64DWSFIG WINBOND [Winbond], W25Q64DWSFIG Datasheet - Page 60

• Manufacturer Part Number: W25Q64DWSFIG
• Description: 1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
• Manufacturer: WINBOND [Winbond]

Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is
a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-0) in the Status
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the
corresponding security register will be permanently locked, Erase Security Register instruction to that
register will be ignored (See 11.1.9 for detail descriptions).
10.2.35 Erase Security Registers (44h)
The W25Q64DW offers four 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four security registers.
The Erase Security Register instruction sequence is shown in Figure 34. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time
duration of t
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0
Security Register #0*
Security Register #1
Security Register #2
Security Register #3
SE
(IO
(IO
CLK
/CS
DO
DI
0
1
(See AC Characteristics). While the Erase Security Register cycle is in progress, the Read
)
)
ADDRESS
Mode 3
Mode 0
*
= MSB
Figure 34. Erase Security Registers Instruction (SPI Mode only)
0
1
Instruction (44h)
2
A23-16
00h
00h
00h
00h
3
4
High Impedance
5
- 60 -
6
A15-12
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
7
23
*
8
22
24-Bit Address
9
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
A11-8
2
29
.
1
30
0
31
W25Q64DW
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Mode 3
Mode 0
A7-0