NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 18

• Manufacturer Part Number: NAND08GW3C2A
• Description: 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

Bus operations
4.5
4.6
Table 4.
1. WP must be V
Table 5.
1. Any additional address input cycles will be ignored.
2. A31 is valid only for the NAND16GW3C2A.
18/58
Bus Cycle
2
3
4
5
1
Command input
nd
Bus operation
st
rd
th
th
Address input
Write protect
Data output
Data input
Standby
For higher frequencies (t
be considered. In this mode, data output is valid on the input/output bus for a time of t
after the falling edge of Read Enable signal (see
See
Write Protect
Write Protect bus operations are used to protect the memory against Program or Erase
operations. When the Write Protect signal is Low the device does not accept Program or
Erase operations, therefore, the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection, even during power-up.
Standby
The memory enters Standby mode by driving Chip Enable, E, High. In Standby mode, the
device is deselected, outputs are disabled and power consumption is reduced.
Bus operations
Address insertion
IH
I/O7
A19
A27
V
V
A7
when issuing a program or erase command.
IL
IL
Table 21
I/O6
A18
A26
for details on the timings requirements.
V
V
A6
V
V
V
V
V
IL
IL
E
X
IH
IL
IL
IL
IL
(1)
RLRL
V
AL
V
V
V
I/O5
A17
A25
V
V
X
X
A5
IH
IL
IL
IL
IL
IL
lower than 30 ns), the Extended Data Out (EDO) mode must
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O4
A16
A24
V
V
A4
IL
IL
Falling
V
V
V
R
X
X
IH
IH
IH
A31
I/O3
A11
A15
A23
A3
Figure
(2)
NAND08GW3C2A, NAND16GW3C2A
Rising
Rising
Rising
V
W
X
X
IH
20).
I/O2
A10
A14
A22
A30
A2
V
IL
WP
X
V
V
/V
X
X
(1)
IH
IL
DD
I/O1
A13
A21
A29
A1
A9
Data output
I/O0 - I/O7
Command
Data input
Address
X
X
I/O0
A12
A20
A28
A0
A8
RLQX