NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 26

• Manufacturer Part Number: NAND08GW3C2A
• Description: 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
Figure 11. Multiplane Page Program
6.8
26/58
RB
I/O
Page Program
Setup Code
80h
2.
As for standard Page Program operations, the device supports Random Data Input during
both data loading phases.
Once the Multiplane Page Program operation has started, maintaining a delay of t
Status Register can be read using the Read Status Register command. Once the Multiplane
Page Program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
If the Multiplane Page Program fails, an error is signaled on bit SR0 of the Status Register.
However, there is no way to identify for which page the program operation failed.
See
Block Erase
Erase operations are done one block at a time. An Erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An Erase operation consists of three steps (refer to
1.
2.
3.
The Erase operation is initiated on the rising edge of write Enable, W, after the Confirm
command is issued. The P/E/R Controller handles Block Erase and implements the verify
process.
During the Block Erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Address Inputs
A19=0
Figure 11
The second step programs, in parallel, the two pages of data loaded into the data buffer
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A31 are used; the other address inputs are ignored.
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
Table 6
Data Input
for a description of Multiplane Page Program waveforms.
for the block addresses of each device.
tBLBH5
Confirm
Code
11h
Busy
Multiplane Page
Program Setup
code
81h
Address Inputs
A19=1
Figure
NAND08GW3C2A, NAND16GW3C2A
Data Input
12):
(Program Busy time)
tBLBH2
Confirm
Code
10h
Busy
Read Status Register
70h
BLBH5
ai13636
SR0
, the