HYI39S128160FT-7 QIMONDA [Qimonda AG], HYI39S128160FT-7 Datasheet - Page 3

• Manufacturer Part Number: HYI39S128160FT-7
• Description: 128-MBit Synchronous DRAM
• Manufacturer: QIMONDA [Qimonda AG]

1
This chapter lists all main features of the product family HY[B/I]39S128[40/80/16][0/7]F[E/T](L) and the ordering information.
1.1
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C Standard Operating Temperature
• -40 to 85 °C Industrial Operating Temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
1.2
The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8
and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip
is fabricated with Qimonda’s advanced 0.11 μm 128-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally
supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply.
All 128-Mbit components are available in P(G)–TSOPII–54 packages.
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
Product Type Speed Code
Speed Grade
Max. Clock Frequency
Overview
Features
Description
@CL3
@CL2
3
• Data Mask for Read / Write control (x4, x8)
• Data Mask for Byte Control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 4096 refresh cycles / 64 ms (15.6 μs)
• Random Column Address every CLK (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Packages: P(G)–TSOPII–54 400 mil width
f
t
t
t
t
CK3
CK3
AC3
CK2
AC2
–7
PC133–222
143
7
5.4
7.5
5.4
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Performance
TABLE 1
Data Sheet
Unit
—
MHz
ns
ns
ns
ns