HYI39S128160FT-7 QIMONDA [Qimonda AG], HYI39S128160FT-7 Datasheet - Page 5

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HYI39S128160FT-7

Manufacturer Part Number
HYI39S128160FT-7
Description
128-MBit Synchronous DRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
2
This chapter contains the pin configuration table, the TSOP package drawing, and the block diagrams for the ×4, ×8, ×16
organization of the SDRAM.
2.1
Listed below are the pin configurations sections for the various signals of the SDRAM
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
Ball No. Name
Clock Signals ×4/×8/×16 Organization
38
37
Control Signals ×4/×8/×16 Organization
18
17
16
19
Address Signals ×4/×8/×16 Organization
20
21
23
24
25
26
29
30
31
32
33
34
22
35
CLK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Chip Configuration
Pin Description
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Buffer
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Function
Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Chip Select
Bank Address Signals 1:0
Address Signal, Address Signal 10/Auto precharge
5
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
Pin Configuration of the SDRAM
128-MBit Synchronous DRAM
TABLE 4
Data Sheet

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