M59DR032A100N1T STMICROELECTRONICS [STMicroelectronics], M59DR032A100N1T Datasheet - Page 18

• Manufacturer Part Number: M59DR032A100N1T
• Description: 32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M59DR032A, M59DR032B
Table 20. Polling and Toggle Bits
STATUS REGISTER BITS
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 bits. Any read attempt within
the Bank being modified and during Program or
Erase command execution will automatically out-
put these five Status Register bits. The P/E.C. au-
tomatically sets bits DQ2, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and should be masked (see Tables 19
and 20). Read attemps within the bank not being
modified will output array data.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7. In
case of a double word program operation, the
complement is done on DQ7 of the last word writ-
ten to the command interface, i.e. the data written
in the fifth cycle. During Erase operation, it outputs
a ’0’. After completion of the operation, DQ7 will
output the bit last programmed or a ’1’ after eras-
ing. Data Polling is valid and only effective during
P/E.C. operation, that is after the fourth W pulse
for programming or after the sixth W pulse for
erase. It must be performed at the address being
programmed or at an address within the block be-
ing erased. See Figure 12 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms. DQ7 will also flag the Erase Suspend mode
by switching from ’0’ to ’1’ at the start of the Erase
Suspend. In order to monitor DQ7 in the Erase
Suspend mode an address within a block being
erased must be provided. For a Read Operation in
18/38
Program
Erase
Erase Suspend Read
(in Erase Suspend
block)
Erase Suspend Read
(outside Erase Suspend
block)
Erase Suspend Program
Mode
DQ7
DQ7
DQ7
DQ7
0
1
Toggle
Toggle
Toggle
DQ6
DQ6
1
Toggle
DQ2
DQ2
N/A
1
1
Suspend mode, DQ7 will output ’1’ if the read is at-
tempted on a block being erased and the data val-
ue on other blocks. During Program operation in
Erase Suspend Mode, DQ7 will have the same be-
haviour as in the normal program execution out-
side of the suspend mode.
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is at V
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. DQ6 will be set to ’1’ if a
Read operation is attempted on an Erase Suspend
block. When erase is suspended DQ6 will toggle
during programming operations in a block different
from the block in Erase Suspend. Either E or G
toggling will cause DQ6 to toggle. See Figure 13
for Toggle Bit flowchart and Figure 11 for Toggle
Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. During Erase Sus-
pend a read from a block being erased will cause
DQ2 to toggle. A read from a block not being
erased will output data. DQ2 will be set to ’1’ during
program operation and to ‘0’ in Erase operation.
After erase completion and if the error bit DQ5 is
set to '1', DQ2 will toggle if the faulty block is ad-
dressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming or block
erase, that results in invalid data in the memory
block. In case of an error in block erase or pro-
gram, the block in which the error occurred or to
which the programmed data belongs, must be dis-
carded. Other Blocks may still be used. The error
bit resets after a Read/Reset (RD) instruction. In
case of success of Program or Erase, the error bit
will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to ‘0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, DQ3 returns to ‘1’, in the range
of 80µs to 120µs.
IL
. The operation is completed