M59DR032A100N1T STMICROELECTRONICS [STMicroelectronics], M59DR032A100N1T Datasheet - Page 7

• Manufacturer Part Number: M59DR032A100N1T
• Description: 32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 8. User Bus Operations
Note: 1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Table 10. Read Block Protection (AS and Read CFI instructions)
Table 11. Read Configuration Register (AS and Read CFI instructions)
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at V
Write Enable W at V
Standby. The memory is in standby when Chip
Enable E is at V
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Manufacturer Code
Device Code
Write
Output Disable
Standby
Reset / Power Down
Block Locking
Protected Block
Unprotected Block
Locked Block
Reset
Reset/Power Down
Block Status
RP Function
Code
Operation
IH
and the P/E.C. is idle. The pow-
M59DR032A
M59DR032B
V
V
V
IH
E
IL
IL
IL
Device
.
V
V
E
V
V
V
G
IL
IL
IL
IL
IL
V
V
V
V
E
X
IH
IL
IL
IL
V
V
V
W
V
V
G
IH
IH
IH
(1)
IL
IL
V
V
V
E
IL
IL
IL
A0
V
V
V
IL
IL
IL
V
V
W
IH
IH
V
V
V
G
IL
IL
IL
V
V
V
A1
V
V
G
IH
IH
IH
X
X
X
IH
IH
IH
V
V
A0
IH
IH
with
V
V
V
W
Block Address
Block Address
Block Address
IH
IH
IH
A20-A12
V
V
A1
IH
IH
V
V
A0
V
IH
IH
IL
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memory is in Power Down
when the Configuration Register is set for Power
Down and RP is at V
reduced to the Power Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to V
V
V
A7-A2
W
X
X
X
IH
IL
0
0
V
V
V
A1
IL
IL
IL
IL
(see Block Lock instruction).
A7-A2
0
0
0
A7-A2
Other Addresses
0
0
0
Don’t Care
Don’t Care
Addresses
RP
V
V
V
V
Don’t Care
Don’t Care
Don’t Care
V
IH
IH
IH
IL
IH
Addresses
Other
Don’t Care
Don’t Care
Don’t Care
Other
M59DR032A, M59DR032B
IL
. The power consumption is
DQ0
X
1
0
WP
DQ15-DQ8 DQ7-DQ0
V
V
V
V
V
DQ10
IH
IH
IH
IH
IL
0
1
00h
00h
00h
DQ1
0
0
1
DQ15-DQ11
DQ15-DQ0
Don’t Care
Don’t Care
Data Input
DQ9-DQ0
DQ15-DQ2
0000h
0000h
0000h
Hi-Z
Hi-Z
Hi-Z
X
A0h
A1h
20h
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