AK4344ET AKM [Asahi Kasei Microsystems], AK4344ET Datasheet - Page 16

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AK4344ET

Manufacturer Part Number
AK4344ET
Description
100dB 96kHz 24-Bit Stereo 3.3V ?? DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
(2) RESET by MCLK stop (PDN pin = “H”)
When MCLK stops, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage.
Notes:
MS0641-E-00
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7μF is attached between VCOM pin and
(2) The analog output corresponding to digital input has the group delay (GD).
(3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section
(4) Click noise occurs in 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal, MCLK inputs and MCLK stops. This noise is
(5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
Internal
D/A In
D/A Out
Clock In
MCLK, BICK, LRCK
PDN pin
External
MUTE
(Digital)
(Analog)
State
VSS.
can be reduced.
output even if “0” data is input.
is shown in this figure.
Power-down
Power-down
(1)
Hi-Z
(6)
(4)
Figure 16. Reset Sequence Example 2
Normal Operation
GD
(2)
- 16 -
(6)
(4)
(5)
MCLK Stop
VCOM
Reset
(3)
(4)
(6)
Normal Operation
GD
(2)
2007/06

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