AK4344ET AKM [Asahi Kasei Microsystems], AK4344ET Datasheet - Page 8

• Manufacturer Part Number: AK4344ET
• Description: 100dB 96kHz 24-Bit Stereo 3.3V ?? DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

(Ta=25°C; VDD=2.7 ∼ 3.6V; C
Parameter
Master Clock Frequency
LRCK Frequency
Audio Interface Timing
Control Interface Timing
Power-Down & Reset Timing
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4344 can be reset by bringing PDN pin = “L”.
MS0641-E-00
Half Speed Mode (512/768/1024/1536fs)
Normal Speed Mode (256/384/512/768fs)
Double Speed Mode (128/192/256/384fs)
Duty Cycle
Half Speed Mode
Normal Speed Mode (DFS1-0 = “00”)
Double Speed Mode
Duty Cycle
BICK Period
BICK Pulse Width Low
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
SDTI Setup Time
PDN Pulse Width
CDTO Delay
Half Speed Mode
Normal Speed Mode
Double Speed Mode
CSN “↑” to CDTO Hi-Z
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C.
When C = 4.7μF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF.
When the states of DIF1-0 pins change, the AK4344 should be reset by PDN pin.
Pulse Width High
Pulse Width High
(DFS1-0 = “10”)
(DFS1-0 = “01”)
L
= 20pF)
SWITCHING CHARACTERISTICS
(Note 11)
(Note 11)
(Note 12)
Symbol
tBCKH
tCCKH
tBCKL
tCCKL
dCLK
dCLK
tCSW
fCLK
fCLK
fCLK
tBCK
tBCK
tBCK
tCCK
tCDH
tDCD
tBLR
tLRB
tSDH
tCDS
tCSH
tCCZ
tSDS
tCSS
tPD
fsh
fsn
fsd
- 8 -
1/128fs
1/128fs
1/64fs
4.096
2.048
6.144
min
200
150
150
40
48
45
70
70
40
40
40
40
80
40
40
50
8
8
80
4
typ
36.864
36.864
36.864
max
60
24
48
96
55
45
70
ms/μF
Units
2007/06
MHz
MHz
MHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%