AK4344ET AKM [Asahi Kasei Microsystems], AK4344ET Datasheet - Page 17

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AK4344ET

Manufacturer Part Number
AK4344ET
Description
100dB 96kHz 24-Bit Stereo 3.3V ?? DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
The AK4344 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire μ P I/F mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “01”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after 16 CCLKs. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
*When the AK4344 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
MS0641-E-00
register is inhibited.
μP Control Interface
WRITE
READ
CCLK
CDTO
CSN
CDTI
CDTI
CDTO
C1-C0: Chip Address: (Fixed to “01”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
C1
C1
0
Figure 17. 4-wire Serial Control I/F Timing
C0
C0
1
R/W
R/W
2
A4
A4
3
A3
A3
4
A2
A2
- 17 -
5
Hi-Z
Hi-Z
A1
A1
6
A0
A0
7
D7
D7
D7
8
D6
D6
D6
9
D5
D5
D5
10 11 12 13
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
14 15
D0
D0
D0
Hi-Z
2007/06

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