SAK-C505L Infineon Technologies AG, SAK-C505L Datasheet - Page 49

• Manufacturer Part Number: SAK-C505L
• Description: 8-bit CMOS Microcontroller
• Manufacturer: Infineon Technologies AG

Fail Save Mechanisms
The C505L offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure:
The watchdog timer in the C505L is a 15-bit timer, which is incremented by a count rate of
up to
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.
Figure 24
Block Diagram of the Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped
during active mode of the device. If the software fails to refresh the running watchdog timer an
internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the
content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh
sequence consists of two consecutive instructions which set the bits WDT and SWDT each. The
reset cause (external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and
power down mode of the processor.
Data Sheet
– a programmable watchdog timer (WDT), with variable time-out period from 192 s up to
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
f
f
OSC
OWDS
OSC
External HW Reset
/192. The system clock of the C505L is divided by two prescalers, a divide-by-two and a
/ 6
SWDT
WDTS
WDT
2
Control Logic
WDT Reset - Request
16
IP0 (A9 )
47
H
IEN0 (A8 )
IEN1 (B8 )
WDTPSEL
H
H
7
0
6
14
WDTREL (86 )
WDTL
WDTH
H
MCB03306
7
8
0
C505L
f
OSC
06.99
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