CD4724BCM Fairchild Semiconductor, CD4724BCM Datasheet

CD4724BCM

Manufacturer Part Number

CD4724BCM

Description

IC ADDRESSABLE LATCH 8BIT 16SOIC

Manufacturer

Fairchild Semiconductor

Series

4000Br

Datasheets

1.CD4724BCM.pdf (7 pages)

2.CD4724BCM.pdf (7 pages)

Specifications of CD4724BCM

Logic Type

D-Type, Addressable

Circuit

1:8

Output Type

Standard

Voltage - Supply

3 V ~ 15 V

Independent Circuits

Delay Time - Propagation

50ns

Current - Output High, Low

8.8mA, 8.8mA

Operating Temperature

-55°C ~ 125°C

Mounting Type

Surface Mount

Package / Case

16-SOIC (3.9mm Width)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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CD4724BCM

CD4724BCN

CD4724BC

8-Bit Addressable Latch

General Description

The CD4724BC is an 8-bit addressable latch with three

address inputs (A0–A2), an active low enable input (E),

active high clear input (CL), a data input (D) and eight out-

puts (Q0–Q7).

Data is entered into a particular bit in the latch when that is

addressed by the address inputs and the enable (E) is

LOW. Data entry is inhibited when enable (E) is HIGH.

When clear (CL) and enable (E) are HIGH, all outputs are

LOW. When clear (CL) is HIGH and enable (E) is LOW, the

channel demultiplexing occurs. The bit that is addressed

has an active output which follows the data input while all

unaddressed bits are held LOW. When operating in the

addressable latch mode (E

than one bit of the address could impose a transient wrong

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Pin Assignments for DIP and SOIC

Package Number

Top View

M16A

N16E

LOW), changing more

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DS006003.prf

address. Therefore, this should only be done while in the

memory mode (E

Features

Truth Table

E CL

Wide supply voltage range:

High noise immunity: 0.45 V

Low power TTL compatibility:

Serial to parallel capability

Storage register capability

Random (addressable) data entry

Active high demultiplexing capability

Common active high clear

fan out of 2 driving 74L or 1 driving 74LS

H Follows Data

H Reset to “0”

L Follows Data

L Hold Previous

Package Description

Data

Addressed

Latch

HIGH, CL

Mode Selection

Holds Previous

Data

Holds Previous

Data

Reset to “0”

Unaddressed

Latch

October 1987

Revised January 1999

LOW).

3.0V to 15V

(typ.)

www.fairchildsemi.com

Addressable

Latch

Memory

Demultiplexer

Clear

Mode

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