CD4043BCN Fairchild Semiconductor, CD4043BCN Datasheet

IC LATCH NOR R/S QUAD 3ST 16-DIP

CD4043BCN

Manufacturer Part Number
CD4043BCN
Description
IC LATCH NOR R/S QUAD 3ST 16-DIP
Manufacturer
Fairchild Semiconductor
Series
4000Br
Datasheet

Specifications of CD4043BCN

Logic Type
S-R Latch
Circuit
1:1
Output Type
Tri-State
Voltage - Supply
3 V ~ 15 V
Independent Circuits
4
Delay Time - Propagation
60ns
Current - Output High, Low
3mA, 6.8mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
4043B
CD4043

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© 2002 Fairchild Semiconductor Corporation
CD4043BCM
CD4043BCN
CD4044BCM
CD4044BCSJ
CD4044BCN
CD4043BC • CD4044BC
Quad 3-STATE NOR R/S Latches •
Quad 3-STATE NAND R/S Latches
General Description
The CD4043BC are quad cross-couple 3-STATE CMOS
NOR latches, and the CD4044BC are quad cross-couple 3-
STATE CMOS NAND latches. Each latch has a separate Q
output and individual SET and RESET inputs. There is a
common 3-STATE ENABLE input for all four latches. A
logic “1” on the ENABLE input connects the latch states to
the Q outputs. A logic “0” on the ENABLE input discon-
nects the latch states from the Q outputs resulting in an
open circuit condition on the Q output. The 3-STATE fea-
ture allows common bussing of the outputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Order Number
Pin Assignments for DIP, SOIC and SOP
Package Number
CD4043BC
Top View
M16A
M16A
M16D
N16E
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005967
Features
Applications
• Multiple bus storage
• Strobed register
• Four bits of independent storage with output enable
• General digital logic
Wide supply voltage range:
Low power: 100 nW (typ.)
High noise immunity: 0.45 V
Separate SET and RESET inputs for each latch
NOR and NAND configuration
3-STATE output with common output enable
Package Description
Pin Assignments for DIP and SOIC
CD4044BC
Top View
October 1987
Revised March 2002
DD
3V to 15V
(typ.)
www.fairchildsemi.com

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CD4043BCN Summary of contents

Page 1

... Ordering Code: Order Number Package Number CD4043BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4044BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ...

Page 2

Block Diagrams CD4043BC Truth Tables CD4043BC 3-STATE NC No change X Don’t care Dominated input Dominated by R ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( (Soldering, 10 seconds) ...

Page 4

AC Electrical Characteristics pF, R 200k, input Symbol Parameter Propagation Delay PLH PHL Propagation Delay Enable to Q (HIGH) ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M16D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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