DM74S373N Fairchild Semiconductor, DM74S373N Datasheet

DM74S373N

Manufacturer Part Number

DM74S373N

Description

IC LATCH OCT D 20-DIP

Manufacturer

Fairchild Semiconductor

Series

74Sr

Datasheet

1.DM74S374N.pdf (7 pages)

Specifications of DM74S373N

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

4.75 V ~ 5.25 V

Independent Circuits

Delay Time - Propagation

12ns

Current - Output High, Low

6.5mA, 20mA

Operating Temperature

0°C ~ 70°C

Mounting Type

Through Hole

Package / Case

20-DIP (0.300", 7.62mm)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74S373
74S373N

Available stocks

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Manufacturer

Quantity

Price

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Bonase Electronics (HK) Co., Limited

Part Number:

DM74S373N

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Quantity:

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DM74S373WM

DM74S373N

DM74S374WM

DM74S374N

DM74S373 • DM74S374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high-logic-level drive provide these registers with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. They are particularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eight latches of the DM74S373 are transparent D-type

latches meaning that while the enable (G) is HIGH the Q

outputs will follow the data (D) inputs. When the enable is

taken LOW the output will be latched at the level of the

data that was set up.

The eight flip-flops of the DM74S374 are edge-triggered D-

type flip-flops. On the positive transition of the clock, the Q

outputs will be set to the logic states that were set up at the

D inputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Order Number

Package Number

DM74S373N

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006486

Schmitt-trigger buffered inputs at the enable/clock lines

simplify system design as ac and dc noise rejection is

improved by typically 400 mV due to the input hysteresis. A

buffered output control input can be used to place the eight

outputs in either a normal logic state (HIGH or LOW logic

levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines signifi-

cantly.

The output control does not affect the internal operation of

the latches or flip-flops. That is, the old data can be

retained or new data can be entered even while the outputs

are OFF.

Features

Choice of 8 latches or 8 D-type flip-flops in a single

package

3-STATE bus-driving outputs

Full parallel-access for loading

Buffered control inputs

P-N-P input reduce D-C loading on data lines

Package Description

DM74S374N

August 1986

Revised May 2000

www.fairchildsemi.com

Related parts for DM74S373N

DM74S373N Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74S373N © 2000 Fairchild Semiconductor Corporation Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis ...

Page 2

Truth Tables DM74S373 Output Enable D Control HIGH Level (Steady State) L LOW Level (Steady State) X Don’t Care Z High Impedance State Transition from LOW-to-HIGH ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range DM74S373 Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level ...

Page 4

DM74S373 Switching Characteristics 5V and Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation ...

Page 5

DM74S374 Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter V Input Clamp Voltage I V HIGH Level OH Output Voltage V LOW Level OL Output Voltage I Input Current @ Max Input Voltage I I ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide www.fairchildsemi.com Package Number M20B 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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