DM74S280N Fairchild Semiconductor, DM74S280N Datasheet

IC GENERATOR/CHECKER 9BIT 14-DIP

DM74S280N

Manufacturer Part Number
DM74S280N
Description
IC GENERATOR/CHECKER 9BIT 14-DIP
Manufacturer
Fairchild Semiconductor
Series
74Sr
Datasheet

Specifications of DM74S280N

Logic Type
Parity Generator/Checker
Number Of Circuits
3
Current - Output High, Low
1mA, 20mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74S280
74S280N

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Part Number
Manufacturer
Quantity
Price
Part Number:
DM74S280N
Manufacturer:
National
Quantity:
3 707
© 2000 Fairchild Semiconductor Corporation
DM74S280M
DM74S280N
DM74S280
9-Bit Parity Generator/Checker
General Description
These universal, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and fea-
ture odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability is eas-
ily expanded by cascading.
The DM74S280 can be used to upgrade the performance
of most systems utilizing the DM74180 parity generator/
checker. Although the DM74S280 is implemented without
expander inputs, the corresponding function is provided by
the availability of all input at pin 4, and no internal connec-
tion at pin 3. This permits the DM74S280 to be substituted
for the 180 in existing designs to produce an identical func-
tion, even if DM74S280’s are mixed with existing 180’s.
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of
unused inputs to used inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006483
Features
Function Table
Generates either odd or even parity for nine data lines
Cascadable for N-bits
Can be used to upgrade existing systems using MSI par-
ity circuits
Typical data-to-output delay—14 ns
(A Thru I) that are HIGH
Package Description
Number of Inputs
0, 2, 4, 6, 8
1, 3, 5, 7, 9
August 1986
Revised May 2000
Even
H
L
www.fairchildsemi.com
Outputs
Odd
H
L

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DM74S280N Summary of contents

Page 1

... Package Number DM74S280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74S280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Diagram Typical Applications Three DM74S280’s can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. (See Figure 1.) FIGURE 1. 25-Line Parity/Generator Checker www.fairchildsemi.com Longer word lengths can be implemented by ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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