MM74C165N Fairchild Semiconductor, MM74C165N Datasheet
MM74C165N
Specifications of MM74C165N
74C165N
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MM74C165N Summary of contents
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... Package Number MM74165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram © 2002 Fairchild Semiconductor Corporation Features Wide supply voltage range: Guaranteed noise margin: 1V High noise immunity: 0.45 V Low power TTL compatibility: fan out of 2 driving 74L ...
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Block Diagrams *Please look into Section 8, Appendix D for availability of various package types. Truth Table State PL Clock1 Parallel Load L X Enable H L Shift (with Ds) H Shift (with Ds) H Hold (Disable Don’t ...
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Absolute Maximum Ratings Voltage at Any Pin 0. Operating Temperature Range Storage Temperature Range Absolute Maximum V CC Power Dissipation Dual-In-Line Small Outline Operating V Range CC Lead Temperature (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply ...
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AC Electrical Characteristics pF, unless otherwise noted A L Symbol Parameter Propagation Delay Time to a Logical “0” pd0 pd1 Logical “1” from Clock or Load ...
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Logic Waveform 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...